THREAD-PARALLEL MPEG-2 AND MPEG-4 ENCODERS FOR SHARED-MEMORY SYSTEM-ON-CHIP MULTIPROCESSORS
This work focuses on speeding up MPEG-2 and MPEG-4 encoding by using thread parallelism for shared-memory, System-on-Chip (SoC) multiprocessors. Improving the performance of the MPEG encoders is shown by reducing the dynamic instruction count at multiple processor contexts and then mapping onto a co...
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| Veröffentlicht in: | International journal of computers & applications 2007, Vol.29 (4), p.353-361 |
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| container_title | International journal of computers & applications |
| container_volume | 29 |
| creator | Chouliaras, V.A. Jacobs, T.R. Núñez-Yanez, J.L. Manolopoulos, K. Nakos, K. Reisis, D. |
| description | This work focuses on speeding up MPEG-2 and MPEG-4 encoding by using thread parallelism for shared-memory, System-on-Chip (SoC) multiprocessors. Improving the performance of the MPEG encoders is shown by reducing the dynamic instruction count at multiple processor contexts and then mapping onto a configurable SoC multiprocessor. The resulting reduction in the dynamic instruction count of the parallelized MPEG-2 TM5 encoder for 32 processor contexts reaches a maximum of 95% and that of the MPEG-4 XViD a maximum of 83% for 16 processor contexts, both compared to the sequential encoder. To realize the parallelized encoders we present a configurable, N-way, extensible, bus-based, cache-coherent SoC multiprocessor, augmented with data-parallel coprocessors, and we give the VLSI implementation for the 2-way and 4-way configurations. |
| doi_str_mv | 10.2316/Journal.202.2007.4.202-2017 |
| format | Article |
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| ispartof | International journal of computers & applications, 2007, Vol.29 (4), p.353-361 |
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| language | eng |
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| source | Taylor & Francis Journals Complete |
| title | THREAD-PARALLEL MPEG-2 AND MPEG-4 ENCODERS FOR SHARED-MEMORY SYSTEM-ON-CHIP MULTIPROCESSORS |
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