Symbolic execution of data paths
We present a data-path model which concisely captures the path constraints imposed by a data-path, such as bus hazards, register constraints, and control encoding limitations. A process for expressing arbitrary datapaths in terms of this model's base components and techniques for systematic tra...
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creator | Monahan, C. Brewer, F. |
description | We present a data-path model which concisely captures the path constraints imposed by a data-path, such as bus hazards, register constraints, and control encoding limitations. A process for expressing arbitrary datapaths in terms of this model's base components and techniques for systematic translation into Boolean functions are described. Finally, this model is expanded to represent the limitations of generating as well as moving operands by incorporating dataflow graphs. The power of this representation is demonstrated by applying the path-constrained model to scheduling on a commercial DSP microprocessor. |
doi_str_mv | 10.1109/GLSV.1995.516029 |
format | Conference Proceeding |
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A process for expressing arbitrary datapaths in terms of this model's base components and techniques for systematic translation into Boolean functions are described. Finally, this model is expanded to represent the limitations of generating as well as moving operands by incorporating dataflow graphs. The power of this representation is demonstrated by applying the path-constrained model to scheduling on a commercial DSP microprocessor.</description><identifier>ISSN: 1066-1395</identifier><identifier>ISBN: 0818670355</identifier><identifier>ISBN: 9780818670350</identifier><identifier>DOI: 10.1109/GLSV.1995.516029</identifier><language>eng</language><publisher>IEEE</publisher><subject>Boolean functions ; Digital signal processing ; Hazards ; Logic ; Microprocessors ; Network synthesis ; Power system modeling ; Processor scheduling ; Registers ; Wires</subject><ispartof>Great Lakes 5th Symposium on VSLI, 1995, p.80-85</ispartof><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/516029$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,780,784,789,790,2056,4048,4049,27924,54919</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/516029$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Monahan, C.</creatorcontrib><creatorcontrib>Brewer, F.</creatorcontrib><title>Symbolic execution of data paths</title><title>Great Lakes 5th Symposium on VSLI</title><addtitle>GLSV</addtitle><description>We present a data-path model which concisely captures the path constraints imposed by a data-path, such as bus hazards, register constraints, and control encoding limitations. A process for expressing arbitrary datapaths in terms of this model's base components and techniques for systematic translation into Boolean functions are described. Finally, this model is expanded to represent the limitations of generating as well as moving operands by incorporating dataflow graphs. The power of this representation is demonstrated by applying the path-constrained model to scheduling on a commercial DSP microprocessor.</description><subject>Boolean functions</subject><subject>Digital signal processing</subject><subject>Hazards</subject><subject>Logic</subject><subject>Microprocessors</subject><subject>Network synthesis</subject><subject>Power system modeling</subject><subject>Processor scheduling</subject><subject>Registers</subject><subject>Wires</subject><issn>1066-1395</issn><isbn>0818670355</isbn><isbn>9780818670350</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>1995</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNotj01Lw0AURQdUsK3uxVVW7hLfZPJmMkspWoWAi6rbMB8vOJI0MZOA_fcW0tXZHM7lMnbHIeMc9OOu2n9lXGvMkEvI9QVbQ8lLqUAgXrIVBylTLjRes3WMPwA5oBArluyPne3b4BL6IzdPoT8kfZN4M5lkMNN3vGFXjWkj3Z65YZ8vzx_b17R6371tn6o05CCmFL0HowqNyqK1jS09FoXxShs8DaGwJbdgubWacifBWKEM8dI7oVxJIMWGPSzdYex_Z4pT3YXoqG3Ngfo51oKjzqXGk3i_iIGI6mEMnRmP9fJa_APg8UpO</recordid><startdate>1995</startdate><enddate>1995</enddate><creator>Monahan, C.</creator><creator>Brewer, F.</creator><general>IEEE</general><scope>6IE</scope><scope>6IL</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIL</scope><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>1995</creationdate><title>Symbolic execution of data paths</title><author>Monahan, C. ; Brewer, F.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-i203t-5dd0a74957b5bbfb8d544ad79a505353b81b0b1bb9e2c60ab37ae18dc37c8e063</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>1995</creationdate><topic>Boolean functions</topic><topic>Digital signal processing</topic><topic>Hazards</topic><topic>Logic</topic><topic>Microprocessors</topic><topic>Network synthesis</topic><topic>Power system modeling</topic><topic>Processor scheduling</topic><topic>Registers</topic><topic>Wires</topic><toplevel>online_resources</toplevel><creatorcontrib>Monahan, C.</creatorcontrib><creatorcontrib>Brewer, F.</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP All) 1998-Present</collection><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Monahan, C.</au><au>Brewer, F.</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Symbolic execution of data paths</atitle><btitle>Great Lakes 5th Symposium on VSLI</btitle><stitle>GLSV</stitle><date>1995</date><risdate>1995</risdate><spage>80</spage><epage>85</epage><pages>80-85</pages><issn>1066-1395</issn><isbn>0818670355</isbn><isbn>9780818670350</isbn><abstract>We present a data-path model which concisely captures the path constraints imposed by a data-path, such as bus hazards, register constraints, and control encoding limitations. A process for expressing arbitrary datapaths in terms of this model's base components and techniques for systematic translation into Boolean functions are described. Finally, this model is expanded to represent the limitations of generating as well as moving operands by incorporating dataflow graphs. The power of this representation is demonstrated by applying the path-constrained model to scheduling on a commercial DSP microprocessor.</abstract><pub>IEEE</pub><doi>10.1109/GLSV.1995.516029</doi><tpages>6</tpages></addata></record> |
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identifier | ISSN: 1066-1395 |
ispartof | Great Lakes 5th Symposium on VSLI, 1995, p.80-85 |
issn | 1066-1395 |
language | eng |
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source | IEEE Electronic Library (IEL) Conference Proceedings |
subjects | Boolean functions Digital signal processing Hazards Logic Microprocessors Network synthesis Power system modeling Processor scheduling Registers Wires |
title | Symbolic execution of data paths |
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