Software Pipelining Irregular Loops On the TMS320C6000 VLIW DSP Architecture

The TMS320C6000 architecture is a leading family of Digital Signal Processors (DSPs). To achieve peak performance, this VLIW architecture relies heavily on software pipelining. Traditionally, software pipelining has been restricted to regular (FOR) loops. More recently, software pipelining has been...

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Bibliographische Detailangaben
Hauptverfasser:	Granston, Elana, Stotzer, Eric, Zbiciak, Joe
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Software and its engineering > Software notations and tools > Compilers > Source code generation
Online-Zugang:	Volltext
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