Enabling energy efficiency in via-patterned gate array devices
In an attempt to enable the cost-effective production of low-and mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architectures. These architectures represent a departure from traditional standard-cell-based ASIC designs in favor of techniques wh...
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| creator | Taylor, R. Reed Schmit, Herman |
| description | In an attempt to enable the cost-effective production of low-and mid-volume application-specific chips, researchers have proposed a number of so-called structured ASIC architectures. These architectures represent a departure from traditional standard-cell-based ASIC designs in favor of techniques which present more physical and structural regularity. If structured ASICs are to become a viable alternative to standard cells, they must deliver performance and energy efficiency which is competitive with standard-cell-based design techniques. This paper focuses on one family of structured ASICs known as via-patterned gate arrays, or VPGAs. In this paper, we present circuit structures and power optimization algorithms which can be applied to VPGA chips in an effort to reduce their operational power dissipation. |
| doi_str_mv | 10.1145/996566.996799 |
| format | Conference Proceeding |
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| identifier | ISBN: 1581138288 |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Applied sciences Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Hardware -- Electronic design automation -- Logic synthesis -- Circuit optimization Hardware -- Very large scale integration design -- Application-specific VLSI designs Integrated circuits Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices |
| title | Enabling energy efficiency in via-patterned gate array devices |
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