Multi-core design automation challenges

The trend to multi-core chip designs presents new challenges for design automation, while the increased reuse of components may offer solutions. This paper describes some of the key challenges with attention paid to three enablers: a physical architecture to streamline chip integration, the linking...

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description The trend to multi-core chip designs presents new challenges for design automation, while the increased reuse of components may offer solutions. This paper describes some of the key challenges with attention paid to three enablers: a physical architecture to streamline chip integration, the linking of early analysis tools around shared data and an updated verification approach for multi-core designs.
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fullrecord <record><control><sourceid>proquest_6IE</sourceid><recordid>TN_cdi_proquest_miscellaneous_31283954</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>4261285</ieee_id><sourcerecordid>31283954</sourcerecordid><originalsourceid>FETCH-LOGICAL-a1694-f28130276949b2f0e08591f02e697d484d609b25b92c698a0f45d8afd8c725a53</originalsourceid><addsrcrecordid>eNqNkDtPwzAUhS0BEqV0ZmDpBCwp1297RBUvqYgFJDbLSexiSOISJwP_HlfpD2A69-p8OsOH0AWGFcaM32IiFVP5ySkkHKEzzDXXVBAJx2gGkqoCA3ycokVKXwCAMVWEyRm6fhmbIRRV7N2ydilsu6Udh9jaIcRuWX3apnHd1qVzdOJtk9zikHP0_nD_tn4qNq-Pz-u7TWGx0KzwRGEKROZbl8SDA8U19kCc0LJmitUCcsFLTSqhlQXPeK2sr1UlCbecztHVtLvr48_o0mDakCrXNLZzcUyGYqKo5iyDlxMYnHNm14fW9r-GEZGB_czN1NqqNWWM38lgMHtX5uDKHFxldPVP1JR9cJ7-AQibZNA</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>conference_proceeding</recordtype><pqid>31283954</pqid></control><display><type>conference_proceeding</type><title>Multi-core design automation challenges</title><source>IEEE Electronic Library (IEL) Conference Proceedings</source><creator>Darringer, John A</creator><creatorcontrib>Darringer, John A</creatorcontrib><description>The trend to multi-core chip designs presents new challenges for design automation, while the increased reuse of components may offer solutions. This paper describes some of the key challenges with attention paid to three enablers: a physical architecture to streamline chip integration, the linking of early analysis tools around shared data and an updated verification approach for multi-core designs.</description><identifier>ISSN: 0738-100X</identifier><identifier>ISBN: 1595936270</identifier><identifier>ISBN: 9781595936271</identifier><identifier>DOI: 10.1145/1278480.1278670</identifier><language>eng</language><publisher>New York, NY, USA: ACM</publisher><subject>Application software ; Application specific integrated circuits ; Applied computing -- Physical sciences and engineering -- Engineering ; Computer systems organization -- Dependable and fault-tolerant systems and networks ; Design ; Design automation ; floorplanning ; General and reference -- Cross-computing tools and techniques -- Performance ; Hardware -- Hardware validation ; Integrated circuit interconnections ; Multi-core systems ; Multicore processing ; Networks -- Network performance evaluation ; Performance analysis ; Permission ; power estimation ; Power system interconnection ; System performance ; thermal analysis ; verification ; Yarn</subject><ispartof>2007 44th ACM/IEEE Design Automation Conference, 2007, p.760-764</ispartof><rights>2007 ACM</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-a1694-f28130276949b2f0e08591f02e697d484d609b25b92c698a0f45d8afd8c725a53</citedby></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/4261285$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,777,781,786,787,793,2052,27906,54739,54901</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/4261285$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Darringer, John A</creatorcontrib><title>Multi-core design automation challenges</title><title>2007 44th ACM/IEEE Design Automation Conference</title><addtitle>DAC</addtitle><description>The trend to multi-core chip designs presents new challenges for design automation, while the increased reuse of components may offer solutions. This paper describes some of the key challenges with attention paid to three enablers: a physical architecture to streamline chip integration, the linking of early analysis tools around shared data and an updated verification approach for multi-core designs.</description><subject>Application software</subject><subject>Application specific integrated circuits</subject><subject>Applied computing -- Physical sciences and engineering -- Engineering</subject><subject>Computer systems organization -- Dependable and fault-tolerant systems and networks</subject><subject>Design</subject><subject>Design automation</subject><subject>floorplanning</subject><subject>General and reference -- Cross-computing tools and techniques -- Performance</subject><subject>Hardware -- Hardware validation</subject><subject>Integrated circuit interconnections</subject><subject>Multi-core systems</subject><subject>Multicore processing</subject><subject>Networks -- Network performance evaluation</subject><subject>Performance analysis</subject><subject>Permission</subject><subject>power estimation</subject><subject>Power system interconnection</subject><subject>System performance</subject><subject>thermal analysis</subject><subject>verification</subject><subject>Yarn</subject><issn>0738-100X</issn><isbn>1595936270</isbn><isbn>9781595936271</isbn><fulltext>true</fulltext><rsrctype>conference_proceeding</rsrctype><creationdate>2007</creationdate><recordtype>conference_proceeding</recordtype><sourceid>6IE</sourceid><sourceid>RIE</sourceid><recordid>eNqNkDtPwzAUhS0BEqV0ZmDpBCwp1297RBUvqYgFJDbLSexiSOISJwP_HlfpD2A69-p8OsOH0AWGFcaM32IiFVP5ySkkHKEzzDXXVBAJx2gGkqoCA3ycokVKXwCAMVWEyRm6fhmbIRRV7N2ydilsu6Udh9jaIcRuWX3apnHd1qVzdOJtk9zikHP0_nD_tn4qNq-Pz-u7TWGx0KzwRGEKROZbl8SDA8U19kCc0LJmitUCcsFLTSqhlQXPeK2sr1UlCbecztHVtLvr48_o0mDakCrXNLZzcUyGYqKo5iyDlxMYnHNm14fW9r-GEZGB_czN1NqqNWWM38lgMHtX5uDKHFxldPVP1JR9cJ7-AQibZNA</recordid><startdate>20070604</startdate><enddate>20070604</enddate><creator>Darringer, John A</creator><general>ACM</general><general>IEEE</general><scope>6IE</scope><scope>6IH</scope><scope>CBEJK</scope><scope>RIE</scope><scope>RIO</scope><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>20070604</creationdate><title>Multi-core design automation challenges</title><author>Darringer, John A</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-a1694-f28130276949b2f0e08591f02e697d484d609b25b92c698a0f45d8afd8c725a53</frbrgroupid><rsrctype>conference_proceedings</rsrctype><prefilter>conference_proceedings</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Application software</topic><topic>Application specific integrated circuits</topic><topic>Applied computing -- Physical sciences and engineering -- Engineering</topic><topic>Computer systems organization -- Dependable and fault-tolerant systems and networks</topic><topic>Design</topic><topic>Design automation</topic><topic>floorplanning</topic><topic>General and reference -- Cross-computing tools and techniques -- Performance</topic><topic>Hardware -- Hardware validation</topic><topic>Integrated circuit interconnections</topic><topic>Multi-core systems</topic><topic>Multicore processing</topic><topic>Networks -- Network performance evaluation</topic><topic>Performance analysis</topic><topic>Permission</topic><topic>power estimation</topic><topic>Power system interconnection</topic><topic>System performance</topic><topic>thermal analysis</topic><topic>verification</topic><topic>Yarn</topic><toplevel>online_resources</toplevel><creatorcontrib>Darringer, John A</creatorcontrib><collection>IEEE Electronic Library (IEL) Conference Proceedings</collection><collection>IEEE Proceedings Order Plan (POP) 1998-present by volume</collection><collection>IEEE Xplore All Conference Proceedings</collection><collection>IEEE Electronic Library (IEL)</collection><collection>IEEE Proceedings Order Plans (POP) 1998-present</collection><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts – Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Darringer, John A</au><format>book</format><genre>proceeding</genre><ristype>CONF</ristype><atitle>Multi-core design automation challenges</atitle><btitle>2007 44th ACM/IEEE Design Automation Conference</btitle><stitle>DAC</stitle><date>2007-06-04</date><risdate>2007</risdate><spage>760</spage><epage>764</epage><pages>760-764</pages><issn>0738-100X</issn><isbn>1595936270</isbn><isbn>9781595936271</isbn><abstract>The trend to multi-core chip designs presents new challenges for design automation, while the increased reuse of components may offer solutions. This paper describes some of the key challenges with attention paid to three enablers: a physical architecture to streamline chip integration, the linking of early analysis tools around shared data and an updated verification approach for multi-core designs.</abstract><cop>New York, NY, USA</cop><pub>ACM</pub><doi>10.1145/1278480.1278670</doi><tpages>5</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 0738-100X
ispartof 2007 44th ACM/IEEE Design Automation Conference, 2007, p.760-764
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source IEEE Electronic Library (IEL) Conference Proceedings
subjects Application software
Application specific integrated circuits
Applied computing -- Physical sciences and engineering -- Engineering
Computer systems organization -- Dependable and fault-tolerant systems and networks
Design
Design automation
floorplanning
General and reference -- Cross-computing tools and techniques -- Performance
Hardware -- Hardware validation
Integrated circuit interconnections
Multi-core systems
Multicore processing
Networks -- Network performance evaluation
Performance analysis
Permission
power estimation
Power system interconnection
System performance
thermal analysis
verification
Yarn
title Multi-core design automation challenges
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-20T11%3A55%3A59IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_6IE&rft_val_fmt=info:ofi/fmt:kev:mtx:book&rft.genre=proceeding&rft.atitle=Multi-core%20design%20automation%20challenges&rft.btitle=2007%2044th%20ACM/IEEE%20Design%20Automation%20Conference&rft.au=Darringer,%20John%20A&rft.date=2007-06-04&rft.spage=760&rft.epage=764&rft.pages=760-764&rft.issn=0738-100X&rft.isbn=1595936270&rft.isbn_list=9781595936271&rft_id=info:doi/10.1145/1278480.1278670&rft_dat=%3Cproquest_6IE%3E31283954%3C/proquest_6IE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=31283954&rft_id=info:pmid/&rft_ieee_id=4261285&rfr_iscdi=true