Efficient use of memory bandwidth to improve network processor throughput

We consider the efficiency of packet buffers used in packet switches built using network processors (NPs). Packet buffers are typically implemented using DRAM, which provides plentiful buffering at a reasonable cost. The problem we address is that a typical NP workload may be unable to utilize the p...

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Bibliographische Detailangaben
Hauptverfasser:	Hasan, Jahangir, Chandra, Satish, Vijaykumar, T. N.
Format:	Tagungsbericht
Sprache:	eng
Schlagworte:	Hardware Hardware > Integrated circuits Hardware > Integrated circuits > Semiconductor memory Hardware > Integrated circuits > Semiconductor memory > Dynamic memory Networks Networks > Network protocols
Online-Zugang:	Volltext
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