IBM's 50 Million gate ASICs
There is no slowdown in the complexity increase for ASIC and SoC designs. As we write this paper in August, 2002, 40M gate ASICs are nearing tape-out, and 50M gate designs are likely to start before this conference takes place. This paper describes the current tool and methodology development effort...
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| creator | Koehl, Juergen Lackey, David E. Doerre, George |
| description | There is no slowdown in the complexity increase for ASIC and SoC designs. As we write this paper in August, 2002, 40M gate ASICs are nearing tape-out, and 50M gate designs are likely to start before this conference takes place. This paper describes the current tool and methodology development efforts focused on enabling ASIC and SoC designs of these sizes and complexity, centered around the reduction of design turn-around-time, improvement of the quality of results and the modeling and optimization of deep sub-micron electrical effects. |
| doi_str_mv | 10.1145/1119772.1119915 |
| format | Conference Proceeding |
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| identifier | ISBN: 0780376609 |
| ispartof | Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003, p.628-634 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) Conference Proceedings |
| subjects | Hardware Hardware -- Electronic design automation Hardware -- Electronic design automation -- Physical design (EDA) Hardware -- Emerging technologies Hardware -- Hardware test Hardware -- Hardware validation Hardware -- Robustness Hardware -- Very large scale integration design |
| title | IBM's 50 Million gate ASICs |
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