Hardware architectures for the Tate pairing over GF(2 m )

In this paper two different approaches to the design of a reconfigurable Tate pairing hardware accelerator are presented. The first uses macro components based on a large, fixed number of underlying Galois Field arithmetic units in parallel to minimise the computation time. The second is an area eff...

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Veröffentlicht in:	Computers & electrical engineering 2007-09, Vol.33 (5), p.392-406
Hauptverfasser:	Keller, Maurice, Ronan, Robert, Marnane, William, Murphy, Colin
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Sprache:	eng
Schlagworte:	BKLS/GHS algorithm Cryptography Hardware architecture Tate pairing
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description	In this paper two different approaches to the design of a reconfigurable Tate pairing hardware accelerator are presented. The first uses macro components based on a large, fixed number of underlying Galois Field arithmetic units in parallel to minimise the computation time. The second is an area efficient approach based on a small, variable number of underlying components. Both architectures are prototyped on an FPGA. Timing results for each architecture with various different design parameters are presented.
doi_str_mv	10.1016/j.compeleceng.2007.05.002
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subjects	BKLS/GHS algorithm Cryptography Hardware architecture Tate pairing
title	Hardware architectures for the Tate pairing over GF(2 m )
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