Evaluating performance of prefetching second level caches
Due to the increasing disparity between processor and main memory system cycle times, many computer systems are now incorporating two levels fo cache memory. Several studies have been done on the design and performance of second level caches, including [3] and [20]. It certainly can and has been sho...
Gespeichert in:
Veröffentlicht in: | Performance evaluation review 1993-05, Vol.20 (4), p.31-42 |
---|---|
Hauptverfasser: | , , |
Format: | Artikel |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 42 |
---|---|
container_issue | 4 |
container_start_page | 31 |
container_title | Performance evaluation review |
container_volume | 20 |
creator | SMITH, R. B ARCHIBALD, J. K NELSON, B. E |
description | Due to the increasing disparity between processor and main memory system cycle times, many computer systems are now incorporating two levels fo cache memory. Several studies have been done on the design and performance of second level caches, including [3] and [20]. It certainly can and has been shown that the addition of a second level of cache enhances the performance of many systems. |
doi_str_mv | 10.1145/155775.155782 |
format | Article |
fullrecord | <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_miscellaneous_29493563</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>29493563</sourcerecordid><originalsourceid>FETCH-LOGICAL-c1423-33832dcc44188dea4c6d65a96c8e52f8ee72903632092455689bdf63cafe85d13</originalsourceid><addsrcrecordid>eNo9kM1Lw0AQxRdRsFaP3nMQb6n7nd2jlPoBBS96XtbJrI1sk7ibFvzvTUjx9AbmN495j5BbRleMSfXAlKoqtZrE8DOymIbSSiPPyYIyLUplrb0kVzl_U8oqzsyC2M3Rx4Mfmvar6DGFLu19C1h0oegTBhxgN60yQtfWRcQjxgI87DBfk4vgY8abky7Jx9Pmff1Sbt-eX9eP2xKY5KIUwgheA0jJjKnRS9C1Vt5qMKh4MIgVt1RowanlUilt7GcdtAAf0KiaiSW5n3371P0cMA9u32TAGH2L3SE7bqUVSosRLGcQUpfz-LzrU7P36dcx6qaC3FyQmwsa-buTsc_gY0hj8Cb_H0mjqZRK_AE12WPH</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>29493563</pqid></control><display><type>article</type><title>Evaluating performance of prefetching second level caches</title><source>ACM Digital Library Complete</source><creator>SMITH, R. B ; ARCHIBALD, J. K ; NELSON, B. E</creator><creatorcontrib>SMITH, R. B ; ARCHIBALD, J. K ; NELSON, B. E</creatorcontrib><description>Due to the increasing disparity between processor and main memory system cycle times, many computer systems are now incorporating two levels fo cache memory. Several studies have been done on the design and performance of second level caches, including [3] and [20]. It certainly can and has been shown that the addition of a second level of cache enhances the performance of many systems.</description><identifier>ISSN: 0163-5999</identifier><identifier>EISSN: 1557-9484</identifier><identifier>DOI: 10.1145/155775.155782</identifier><identifier>CODEN: PEREDN</identifier><language>eng</language><publisher>New York, NY: Association for Computing Machinery</publisher><subject>Applied sciences ; Computer science; control theory; systems ; Computer systems performance. Reliability ; Exact sciences and technology ; Software</subject><ispartof>Performance evaluation review, 1993-05, Vol.20 (4), p.31-42</ispartof><rights>1993 INIST-CNRS</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c1423-33832dcc44188dea4c6d65a96c8e52f8ee72903632092455689bdf63cafe85d13</citedby><cites>FETCH-LOGICAL-c1423-33832dcc44188dea4c6d65a96c8e52f8ee72903632092455689bdf63cafe85d13</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,780,784,27923,27924</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=4860445$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>SMITH, R. B</creatorcontrib><creatorcontrib>ARCHIBALD, J. K</creatorcontrib><creatorcontrib>NELSON, B. E</creatorcontrib><title>Evaluating performance of prefetching second level caches</title><title>Performance evaluation review</title><description>Due to the increasing disparity between processor and main memory system cycle times, many computer systems are now incorporating two levels fo cache memory. Several studies have been done on the design and performance of second level caches, including [3] and [20]. It certainly can and has been shown that the addition of a second level of cache enhances the performance of many systems.</description><subject>Applied sciences</subject><subject>Computer science; control theory; systems</subject><subject>Computer systems performance. Reliability</subject><subject>Exact sciences and technology</subject><subject>Software</subject><issn>0163-5999</issn><issn>1557-9484</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1993</creationdate><recordtype>article</recordtype><recordid>eNo9kM1Lw0AQxRdRsFaP3nMQb6n7nd2jlPoBBS96XtbJrI1sk7ibFvzvTUjx9AbmN495j5BbRleMSfXAlKoqtZrE8DOymIbSSiPPyYIyLUplrb0kVzl_U8oqzsyC2M3Rx4Mfmvar6DGFLu19C1h0oegTBhxgN60yQtfWRcQjxgI87DBfk4vgY8abky7Jx9Pmff1Sbt-eX9eP2xKY5KIUwgheA0jJjKnRS9C1Vt5qMKh4MIgVt1RowanlUilt7GcdtAAf0KiaiSW5n3371P0cMA9u32TAGH2L3SE7bqUVSosRLGcQUpfz-LzrU7P36dcx6qaC3FyQmwsa-buTsc_gY0hj8Cb_H0mjqZRK_AE12WPH</recordid><startdate>19930501</startdate><enddate>19930501</enddate><creator>SMITH, R. B</creator><creator>ARCHIBALD, J. K</creator><creator>NELSON, B. E</creator><general>Association for Computing Machinery</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>19930501</creationdate><title>Evaluating performance of prefetching second level caches</title><author>SMITH, R. B ; ARCHIBALD, J. K ; NELSON, B. E</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c1423-33832dcc44188dea4c6d65a96c8e52f8ee72903632092455689bdf63cafe85d13</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1993</creationdate><topic>Applied sciences</topic><topic>Computer science; control theory; systems</topic><topic>Computer systems performance. Reliability</topic><topic>Exact sciences and technology</topic><topic>Software</topic><toplevel>online_resources</toplevel><creatorcontrib>SMITH, R. B</creatorcontrib><creatorcontrib>ARCHIBALD, J. K</creatorcontrib><creatorcontrib>NELSON, B. E</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>Performance evaluation review</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>SMITH, R. B</au><au>ARCHIBALD, J. K</au><au>NELSON, B. E</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Evaluating performance of prefetching second level caches</atitle><jtitle>Performance evaluation review</jtitle><date>1993-05-01</date><risdate>1993</risdate><volume>20</volume><issue>4</issue><spage>31</spage><epage>42</epage><pages>31-42</pages><issn>0163-5999</issn><eissn>1557-9484</eissn><coden>PEREDN</coden><abstract>Due to the increasing disparity between processor and main memory system cycle times, many computer systems are now incorporating two levels fo cache memory. Several studies have been done on the design and performance of second level caches, including [3] and [20]. It certainly can and has been shown that the addition of a second level of cache enhances the performance of many systems.</abstract><cop>New York, NY</cop><pub>Association for Computing Machinery</pub><doi>10.1145/155775.155782</doi><tpages>12</tpages></addata></record> |
fulltext | fulltext |
identifier | ISSN: 0163-5999 |
ispartof | Performance evaluation review, 1993-05, Vol.20 (4), p.31-42 |
issn | 0163-5999 1557-9484 |
language | eng |
recordid | cdi_proquest_miscellaneous_29493563 |
source | ACM Digital Library Complete |
subjects | Applied sciences Computer science control theory systems Computer systems performance. Reliability Exact sciences and technology Software |
title | Evaluating performance of prefetching second level caches |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-11T01%3A11%3A24IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Evaluating%20performance%20of%20prefetching%20second%20level%20caches&rft.jtitle=Performance%20evaluation%20review&rft.au=SMITH,%20R.%20B&rft.date=1993-05-01&rft.volume=20&rft.issue=4&rft.spage=31&rft.epage=42&rft.pages=31-42&rft.issn=0163-5999&rft.eissn=1557-9484&rft.coden=PEREDN&rft_id=info:doi/10.1145/155775.155782&rft_dat=%3Cproquest_cross%3E29493563%3C/proquest_cross%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=29493563&rft_id=info:pmid/&rfr_iscdi=true |