Realizing high IPC through a scalable memory-latency tolerant multipath microarchitecture

A microarchitecture is described that achieves high performance on conventional single-threaded program codes without compiler assistance. To obtain high instructions per clock (IPC) for inherently sequential (e.g., SpecInt-2000 programs), a large number of instructions must be in flight simultaneou...

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Veröffentlicht in:	Computer architecture news 2003-03, Vol.31 (1), p.16-25
Hauptverfasser:	Morano, D., Khalafi, A., Kaeli, D. R., Uht, A. K.
Format:	Artikel
Sprache:	eng
Online-Zugang:	Volltext
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