An area-efficient bit-serial integer and GF(2 n ) multiplier

This paper presents the design of a new multiplier architecture for normal integer multiplication of positive and negative numbers as well as for multiplication in finite fields of order 2 n . It has been developed to increase the performance of algorithms for cryptographic and signal processing applications on implementations of the Instruction Systolic Array (ISA) parallel computer model [M. Kunde, H.W. Lang, M. Schimmler, H. Schmeck, H. Schröder, Parallel Computing 7 (1988) 25–39, H.W. Lang, Integration, the VLSI Journal 4 (1986) 65–74]. The multiplier operates least significant bit (LSB)-first for integer multiplication and most significant bit ( )-first for finite field multiplication. It is a modular bit-serial design, which on the one hand can be efficiently implemented in hardware and on the other hand has the advantage that it can handle operands of arbitrary length.