Analysis of the impact of proximity correction algorithms on circuit performance
Variation in channel length degrades circuit reliability and yield. A common way to compensate for this problem is to increase the mean channel length, which, unfortunately, degrades circuit performance for digital circuits. One source of channel length variation is lithography, during which the lin...
Gespeichert in:
Veröffentlicht in: | IEEE transactions on semiconductor manufacturing 1999-08, Vol.12 (3), p.313-322 |
---|---|
Hauptverfasser: | , , , , |
Format: | Artikel |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 322 |
---|---|
container_issue | 3 |
container_start_page | 313 |
container_title | IEEE transactions on semiconductor manufacturing |
container_volume | 12 |
creator | Li Chen Milor, L.S. Ouyang, C.H. Maly, W. Yeng-Kaung Peng |
description | Variation in channel length degrades circuit reliability and yield. A common way to compensate for this problem is to increase the mean channel length, which, unfortunately, degrades circuit performance for digital circuits. One source of channel length variation is lithography, during which the line width is influenced by local layout patterns. It is possible to compensate for this effect by resizing transistor gates appropriately on the mask. However, the effectiveness of the correction is limited by constraints such as the mask correction resolution. To determine how to design a good correction scheme with limited resources, we have developed a method to compare different correction algorithms in terms of their impact on the performance of one of the main functional blocks in a state-of-the-art microprocessor. In particular, to evaluate correction algorithms while avoiding the high cost associated with generating multiple mask sets and fabricating product wafers with each of these mask sets, we present a method for predicting the correction results using simulation. Our methodology involves a DRC-based approach for gate resizing, along with critical path simulation for evaluating circuit performance. In-line CD measurement data were used to measure the impact of the proximity effect on transistor channel length. Electrical test results were used to calibrate the device models for circuit simulation. |
doi_str_mv | 10.1109/66.778196 |
format | Article |
fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_29414684</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>778196</ieee_id><sourcerecordid>29414684</sourcerecordid><originalsourceid>FETCH-LOGICAL-c400t-93d152f5120b52df6ff388d83917fc90021b751de06aee542faf48ccfc95e70f3</originalsourceid><addsrcrecordid>eNqF0UtLAzEQB_AgCtbqwaunPYjiYeskm-dRii8o6EHPS5pNbGRfJluw396ULXqzpzDMb4bwH4TOMcwwBnXL-UwIiRU_QBPMmMxJQdkhmoBUNOcMxDE6ifETAFOqxAS93rW63kQfs85lw8pmvum1GbZVH7pv3_hhk5kuBGsG37WZrj-64IdVkwbazPhg1n7IehtcFxrdGnuKjpyuoz3bvVP0_nD_Nn_KFy-Pz_O7RW4owJCrosKMOIYJLBmpHHeukLKShcLCGQVA8FIwXFng2lpGidOOSmNSj1kBrpii63Fv-ubX2sahbHw0tq51a7t1LBVWKgVSqCSv_pVEUUy5pPthMkwB3w8FEEmAJHgzQhO6GIN1ZR98o8OmxFBu71VyXo73SvZyt1RHo2sXUpo-_g2kTLjAiV2MzFtrf7u7HT9Ifpyk</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>27028202</pqid></control><display><type>article</type><title>Analysis of the impact of proximity correction algorithms on circuit performance</title><source>IEEE Electronic Library (IEL)</source><creator>Li Chen ; Milor, L.S. ; Ouyang, C.H. ; Maly, W. ; Yeng-Kaung Peng</creator><creatorcontrib>Li Chen ; Milor, L.S. ; Ouyang, C.H. ; Maly, W. ; Yeng-Kaung Peng</creatorcontrib><description>Variation in channel length degrades circuit reliability and yield. A common way to compensate for this problem is to increase the mean channel length, which, unfortunately, degrades circuit performance for digital circuits. One source of channel length variation is lithography, during which the line width is influenced by local layout patterns. It is possible to compensate for this effect by resizing transistor gates appropriately on the mask. However, the effectiveness of the correction is limited by constraints such as the mask correction resolution. To determine how to design a good correction scheme with limited resources, we have developed a method to compare different correction algorithms in terms of their impact on the performance of one of the main functional blocks in a state-of-the-art microprocessor. In particular, to evaluate correction algorithms while avoiding the high cost associated with generating multiple mask sets and fabricating product wafers with each of these mask sets, we present a method for predicting the correction results using simulation. Our methodology involves a DRC-based approach for gate resizing, along with critical path simulation for evaluating circuit performance. In-line CD measurement data were used to measure the impact of the proximity effect on transistor channel length. Electrical test results were used to calibrate the device models for circuit simulation.</description><identifier>ISSN: 0894-6507</identifier><identifier>EISSN: 1558-2345</identifier><identifier>DOI: 10.1109/66.778196</identifier><identifier>CODEN: ITSMED</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Algorithm design and analysis ; Algorithms ; Applied sciences ; Channels ; Circuit optimization ; Circuit simulation ; Circuit testing ; Circuits ; Computer simulation ; Costs ; Degradation ; Design. Technologies. Operation analysis. Testing ; Digital circuits ; Electronics ; Exact sciences and technology ; Gates (circuits) ; Integrated circuits ; Length measurement ; Lithography ; Masks ; Microelectronic fabrication (materials and surfaces technology) ; Microprocessors ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Semiconductors</subject><ispartof>IEEE transactions on semiconductor manufacturing, 1999-08, Vol.12 (3), p.313-322</ispartof><rights>1999 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c400t-93d152f5120b52df6ff388d83917fc90021b751de06aee542faf48ccfc95e70f3</citedby><cites>FETCH-LOGICAL-c400t-93d152f5120b52df6ff388d83917fc90021b751de06aee542faf48ccfc95e70f3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/778196$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>309,310,314,780,784,789,790,796,23929,23930,25139,27923,27924,54757</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/778196$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=1900671$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Li Chen</creatorcontrib><creatorcontrib>Milor, L.S.</creatorcontrib><creatorcontrib>Ouyang, C.H.</creatorcontrib><creatorcontrib>Maly, W.</creatorcontrib><creatorcontrib>Yeng-Kaung Peng</creatorcontrib><title>Analysis of the impact of proximity correction algorithms on circuit performance</title><title>IEEE transactions on semiconductor manufacturing</title><addtitle>TSM</addtitle><description>Variation in channel length degrades circuit reliability and yield. A common way to compensate for this problem is to increase the mean channel length, which, unfortunately, degrades circuit performance for digital circuits. One source of channel length variation is lithography, during which the line width is influenced by local layout patterns. It is possible to compensate for this effect by resizing transistor gates appropriately on the mask. However, the effectiveness of the correction is limited by constraints such as the mask correction resolution. To determine how to design a good correction scheme with limited resources, we have developed a method to compare different correction algorithms in terms of their impact on the performance of one of the main functional blocks in a state-of-the-art microprocessor. In particular, to evaluate correction algorithms while avoiding the high cost associated with generating multiple mask sets and fabricating product wafers with each of these mask sets, we present a method for predicting the correction results using simulation. Our methodology involves a DRC-based approach for gate resizing, along with critical path simulation for evaluating circuit performance. In-line CD measurement data were used to measure the impact of the proximity effect on transistor channel length. Electrical test results were used to calibrate the device models for circuit simulation.</description><subject>Algorithm design and analysis</subject><subject>Algorithms</subject><subject>Applied sciences</subject><subject>Channels</subject><subject>Circuit optimization</subject><subject>Circuit simulation</subject><subject>Circuit testing</subject><subject>Circuits</subject><subject>Computer simulation</subject><subject>Costs</subject><subject>Degradation</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Gates (circuits)</subject><subject>Integrated circuits</subject><subject>Length measurement</subject><subject>Lithography</subject><subject>Masks</subject><subject>Microelectronic fabrication (materials and surfaces technology)</subject><subject>Microprocessors</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Semiconductors</subject><issn>0894-6507</issn><issn>1558-2345</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1999</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqF0UtLAzEQB_AgCtbqwaunPYjiYeskm-dRii8o6EHPS5pNbGRfJluw396ULXqzpzDMb4bwH4TOMcwwBnXL-UwIiRU_QBPMmMxJQdkhmoBUNOcMxDE6ifETAFOqxAS93rW63kQfs85lw8pmvum1GbZVH7pv3_hhk5kuBGsG37WZrj-64IdVkwbazPhg1n7IehtcFxrdGnuKjpyuoz3bvVP0_nD_Nn_KFy-Pz_O7RW4owJCrosKMOIYJLBmpHHeukLKShcLCGQVA8FIwXFng2lpGidOOSmNSj1kBrpii63Fv-ubX2sahbHw0tq51a7t1LBVWKgVSqCSv_pVEUUy5pPthMkwB3w8FEEmAJHgzQhO6GIN1ZR98o8OmxFBu71VyXo73SvZyt1RHo2sXUpo-_g2kTLjAiV2MzFtrf7u7HT9Ifpyk</recordid><startdate>19990801</startdate><enddate>19990801</enddate><creator>Li Chen</creator><creator>Milor, L.S.</creator><creator>Ouyang, C.H.</creator><creator>Maly, W.</creator><creator>Yeng-Kaung Peng</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope><scope>7SP</scope><scope>7TB</scope><scope>FR3</scope><scope>F28</scope></search><sort><creationdate>19990801</creationdate><title>Analysis of the impact of proximity correction algorithms on circuit performance</title><author>Li Chen ; Milor, L.S. ; Ouyang, C.H. ; Maly, W. ; Yeng-Kaung Peng</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c400t-93d152f5120b52df6ff388d83917fc90021b751de06aee542faf48ccfc95e70f3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1999</creationdate><topic>Algorithm design and analysis</topic><topic>Algorithms</topic><topic>Applied sciences</topic><topic>Channels</topic><topic>Circuit optimization</topic><topic>Circuit simulation</topic><topic>Circuit testing</topic><topic>Circuits</topic><topic>Computer simulation</topic><topic>Costs</topic><topic>Degradation</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Digital circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Gates (circuits)</topic><topic>Integrated circuits</topic><topic>Length measurement</topic><topic>Lithography</topic><topic>Masks</topic><topic>Microelectronic fabrication (materials and surfaces technology)</topic><topic>Microprocessors</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Semiconductors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Li Chen</creatorcontrib><creatorcontrib>Milor, L.S.</creatorcontrib><creatorcontrib>Ouyang, C.H.</creatorcontrib><creatorcontrib>Maly, W.</creatorcontrib><creatorcontrib>Yeng-Kaung Peng</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Electronics & Communications Abstracts</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Engineering Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><jtitle>IEEE transactions on semiconductor manufacturing</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Li Chen</au><au>Milor, L.S.</au><au>Ouyang, C.H.</au><au>Maly, W.</au><au>Yeng-Kaung Peng</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Analysis of the impact of proximity correction algorithms on circuit performance</atitle><jtitle>IEEE transactions on semiconductor manufacturing</jtitle><stitle>TSM</stitle><date>1999-08-01</date><risdate>1999</risdate><volume>12</volume><issue>3</issue><spage>313</spage><epage>322</epage><pages>313-322</pages><issn>0894-6507</issn><eissn>1558-2345</eissn><coden>ITSMED</coden><abstract>Variation in channel length degrades circuit reliability and yield. A common way to compensate for this problem is to increase the mean channel length, which, unfortunately, degrades circuit performance for digital circuits. One source of channel length variation is lithography, during which the line width is influenced by local layout patterns. It is possible to compensate for this effect by resizing transistor gates appropriately on the mask. However, the effectiveness of the correction is limited by constraints such as the mask correction resolution. To determine how to design a good correction scheme with limited resources, we have developed a method to compare different correction algorithms in terms of their impact on the performance of one of the main functional blocks in a state-of-the-art microprocessor. In particular, to evaluate correction algorithms while avoiding the high cost associated with generating multiple mask sets and fabricating product wafers with each of these mask sets, we present a method for predicting the correction results using simulation. Our methodology involves a DRC-based approach for gate resizing, along with critical path simulation for evaluating circuit performance. In-line CD measurement data were used to measure the impact of the proximity effect on transistor channel length. Electrical test results were used to calibrate the device models for circuit simulation.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/66.778196</doi><tpages>10</tpages></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 0894-6507 |
ispartof | IEEE transactions on semiconductor manufacturing, 1999-08, Vol.12 (3), p.313-322 |
issn | 0894-6507 1558-2345 |
language | eng |
recordid | cdi_proquest_miscellaneous_29414684 |
source | IEEE Electronic Library (IEL) |
subjects | Algorithm design and analysis Algorithms Applied sciences Channels Circuit optimization Circuit simulation Circuit testing Circuits Computer simulation Costs Degradation Design. Technologies. Operation analysis. Testing Digital circuits Electronics Exact sciences and technology Gates (circuits) Integrated circuits Length measurement Lithography Masks Microelectronic fabrication (materials and surfaces technology) Microprocessors Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Semiconductors |
title | Analysis of the impact of proximity correction algorithms on circuit performance |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-08T06%3A34%3A48IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Analysis%20of%20the%20impact%20of%20proximity%20correction%20algorithms%20on%20circuit%20performance&rft.jtitle=IEEE%20transactions%20on%20semiconductor%20manufacturing&rft.au=Li%20Chen&rft.date=1999-08-01&rft.volume=12&rft.issue=3&rft.spage=313&rft.epage=322&rft.pages=313-322&rft.issn=0894-6507&rft.eissn=1558-2345&rft.coden=ITSMED&rft_id=info:doi/10.1109/66.778196&rft_dat=%3Cproquest_RIE%3E29414684%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=27028202&rft_id=info:pmid/&rft_ieee_id=778196&rfr_iscdi=true |