FPGA implementations of the ICEBERG block cipher
This paper presents field programmable gate array (FPGA) implementations of ICEBERG, a block cipher designed for reconfigurable hardware implementations and presented at FSE 2004. All its components are involutional and allow very efficient combinations of encryption/decryption. The implementations...
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| Veröffentlicht in: | Integration (Amsterdam) 2007, Vol.40 (1), p.20-27 |
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| container_title | Integration (Amsterdam) |
| container_volume | 40 |
| creator | Standaert, F.-X. Piret, G. Rouvroy, G. Quisquater, J.-J. |
| description | This paper presents field programmable gate array (FPGA) implementations of
ICEBERG, a block cipher designed for reconfigurable hardware implementations and presented at FSE 2004. All its components are involutional and allow very efficient combinations of encryption/decryption. The implementations proposed also allow changing the key and encrypt/decrypt
(
E
/
D
)
mode for every plain text, without any performance loss. In comparison with other recent block ciphers, the implementation results of
ICEBERG show a significant improvement of hardware efficiency. Moreover, the key and
E
/
D
agility allow considering new encryption modes to counteract certain side-channel attacks. |
| doi_str_mv | 10.1016/j.vlsi.2005.12.008 |
| format | Article |
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ICEBERG, a block cipher designed for reconfigurable hardware implementations and presented at FSE 2004. All its components are involutional and allow very efficient combinations of encryption/decryption. The implementations proposed also allow changing the key and encrypt/decrypt
(
E
/
D
)
mode for every plain text, without any performance loss. In comparison with other recent block ciphers, the implementation results of
ICEBERG show a significant improvement of hardware efficiency. Moreover, the key and
E
/
D
agility allow considering new encryption modes to counteract certain side-channel attacks.</description><identifier>ISSN: 0167-9260</identifier><identifier>EISSN: 1872-7522</identifier><identifier>DOI: 10.1016/j.vlsi.2005.12.008</identifier><identifier>CODEN: IVJODL</identifier><language>eng</language><publisher>Amsterdam: Elsevier B.V</publisher><subject>Applied sciences ; Block ciphers ; Circuit properties ; Digital circuits ; Electric, optical and optoelectronic circuits ; Electronic circuits ; Electronics ; Exact sciences and technology ; FPGAs ; Hardware implementations</subject><ispartof>Integration (Amsterdam), 2007, Vol.40 (1), p.20-27</ispartof><rights>2006 Elsevier B.V.</rights><rights>2007 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c361t-90bddaed8953112fa9621607ec32906b6e4ecebb967996725e7e639b9e603c023</citedby><cites>FETCH-LOGICAL-c361t-90bddaed8953112fa9621607ec32906b6e4ecebb967996725e7e639b9e603c023</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://dx.doi.org/10.1016/j.vlsi.2005.12.008$$EHTML$$P50$$Gelsevier$$H</linktohtml><link.rule.ids>314,777,781,3537,4010,27904,27905,27906,45976</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=18397212$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Standaert, F.-X.</creatorcontrib><creatorcontrib>Piret, G.</creatorcontrib><creatorcontrib>Rouvroy, G.</creatorcontrib><creatorcontrib>Quisquater, J.-J.</creatorcontrib><title>FPGA implementations of the ICEBERG block cipher</title><title>Integration (Amsterdam)</title><description>This paper presents field programmable gate array (FPGA) implementations of
ICEBERG, a block cipher designed for reconfigurable hardware implementations and presented at FSE 2004. All its components are involutional and allow very efficient combinations of encryption/decryption. The implementations proposed also allow changing the key and encrypt/decrypt
(
E
/
D
)
mode for every plain text, without any performance loss. In comparison with other recent block ciphers, the implementation results of
ICEBERG show a significant improvement of hardware efficiency. Moreover, the key and
E
/
D
agility allow considering new encryption modes to counteract certain side-channel attacks.</description><subject>Applied sciences</subject><subject>Block ciphers</subject><subject>Circuit properties</subject><subject>Digital circuits</subject><subject>Electric, optical and optoelectronic circuits</subject><subject>Electronic circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>FPGAs</subject><subject>Hardware implementations</subject><issn>0167-9260</issn><issn>1872-7522</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2007</creationdate><recordtype>article</recordtype><recordid>eNp9kDFPwzAQhS0EEqXwB5iywJZwdho7llhK1ZZKlUAIZstxLqpLEgc7VOLfk6iV2BhOt3zv3b1HyC2FhALlD_vkUAebMIAsoSwByM_IhOaCxSJj7JxMBkjEknG4JFch7AGAzkQ2IbB6Xc8j23Q1Ntj2ureuDZGron6H0WaxfFq-raOiduYzMrbbob8mF5WuA96c9pR8rJbvi-d4-7LeLObb2KSc9rGEoiw1lrnMUkpZpSVnlINAkzIJvOA4Q4NFIbmQw7AMBfJUFhI5pAZYOiX3R9_Ou69vDL1qbDBY17pF9x0UG8LQTMAAsiNovAvBY6U6bxvtfxQFNZaj9mosR43lKMrUUM4guju562B0XXndGhv-lHkqBaPjF49HDoeoB4teBWOxNVhaj6ZXpbP_nfkF0tV4CQ</recordid><startdate>2007</startdate><enddate>2007</enddate><creator>Standaert, F.-X.</creator><creator>Piret, G.</creator><creator>Rouvroy, G.</creator><creator>Quisquater, J.-J.</creator><general>Elsevier B.V</general><general>Elsevier Science</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>2007</creationdate><title>FPGA implementations of the ICEBERG block cipher</title><author>Standaert, F.-X. ; Piret, G. ; Rouvroy, G. ; Quisquater, J.-J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c361t-90bddaed8953112fa9621607ec32906b6e4ecebb967996725e7e639b9e603c023</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2007</creationdate><topic>Applied sciences</topic><topic>Block ciphers</topic><topic>Circuit properties</topic><topic>Digital circuits</topic><topic>Electric, optical and optoelectronic circuits</topic><topic>Electronic circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>FPGAs</topic><topic>Hardware implementations</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Standaert, F.-X.</creatorcontrib><creatorcontrib>Piret, G.</creatorcontrib><creatorcontrib>Rouvroy, G.</creatorcontrib><creatorcontrib>Quisquater, J.-J.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>Integration (Amsterdam)</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Standaert, F.-X.</au><au>Piret, G.</au><au>Rouvroy, G.</au><au>Quisquater, J.-J.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>FPGA implementations of the ICEBERG block cipher</atitle><jtitle>Integration (Amsterdam)</jtitle><date>2007</date><risdate>2007</risdate><volume>40</volume><issue>1</issue><spage>20</spage><epage>27</epage><pages>20-27</pages><issn>0167-9260</issn><eissn>1872-7522</eissn><coden>IVJODL</coden><abstract>This paper presents field programmable gate array (FPGA) implementations of
ICEBERG, a block cipher designed for reconfigurable hardware implementations and presented at FSE 2004. All its components are involutional and allow very efficient combinations of encryption/decryption. The implementations proposed also allow changing the key and encrypt/decrypt
(
E
/
D
)
mode for every plain text, without any performance loss. In comparison with other recent block ciphers, the implementation results of
ICEBERG show a significant improvement of hardware efficiency. Moreover, the key and
E
/
D
agility allow considering new encryption modes to counteract certain side-channel attacks.</abstract><cop>Amsterdam</cop><pub>Elsevier B.V</pub><doi>10.1016/j.vlsi.2005.12.008</doi><tpages>8</tpages></addata></record> |
| fulltext | fulltext |
| identifier | ISSN: 0167-9260 |
| ispartof | Integration (Amsterdam), 2007, Vol.40 (1), p.20-27 |
| issn | 0167-9260 1872-7522 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_29261570 |
| source | Elsevier ScienceDirect Journals |
| subjects | Applied sciences Block ciphers Circuit properties Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology FPGAs Hardware implementations |
| title | FPGA implementations of the ICEBERG block cipher |
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