Cover Picture: Complementary Symmetry Silicon Nanowire Logic: Power-Efficient Inverters with Gain (Small 10/2006)

The cover picture illustrates a complementary symmetry‐based inverter logic gate fabricated from dense arrays of silicon nanowires. Such logic circuits are highly energy efficient and exhibit gain, but require both p‐type and n‐type transistors (represented as the dark green and orange wires in the central drawing). The upper‐left electron micrograph shows an array of the 15‐nm‐wide silicon nanowires that were utilized to make the inverters. The upper‐right trace represents the output of the inverter: as the input ( x axis) voltage is increased, the output voltage ( y axis) switches from high to low. The background and bottom‐right micrographs are images of the actual circuits. For more information, please read the Communication “Complementary Symmetry Silicon Nanowire Logic: Power‐Efficient Inverters with Gain” by J. R. Heath and co‐workers on page 1153 ff.