The effect of drain offset on current-voltage characteristics in sub micron polysilicon thin-film transistors

The effect of drain offset on current-voltage characteristics in sub micron polysilicon thin-film transistors

We have examined the effect of drain offset structures with lengths ranging from 0.0 /spl mu/m to 1.0 /spl mu/m on submicron polysilicon TFT devices. The drain offset was found to exhibit resistive behavior that tends to lower the TFT drive current as it reduces the leakage current. For the range of...

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Veröffentlicht in:IEEE transactions on electron devices 1996-08, Vol.43 (8), p.1306-1308
Hauptverfasser: Olasupo, K.R., Yarbrough, W., Hatalis, M.K.
Format: Artikel
Sprache:eng
Schlagworte:
Active matrix liquid crystal displays
Computer science
Doping
Flexible printed circuits
Leakage current
Silicon
Substrates
Thin film devices
Thin film transistors
Voltage
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Zusammenfassung:We have examined the effect of drain offset structures with lengths ranging from 0.0 /spl mu/m to 1.0 /spl mu/m on submicron polysilicon TFT devices. The drain offset was found to exhibit resistive behavior that tends to lower the TFT drive current as it reduces the leakage current. For the range of channel lengths studied (1.0 /spl mu/m to 0.35 /spl mu/m) the optimum drain offset length was 0.35 /spl mu/m.
ISSN:0018-9383
1557-9646
DOI:10.1109/16.506785