A technique to generate feasible tests for communications systems with multiple timers
We present a new model for testing real-time protocols with multiple timers, which captures complex timing dependencies by using simple linear expressions involving timer-related variables. This new modeling technique, combined with the algorithms to eliminate inconsistencies, allows generation of f...
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| Veröffentlicht in: | IEEE/ACM transactions on networking 2003-10, Vol.11 (5), p.796-809 |
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| container_title | IEEE/ACM transactions on networking |
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| creator | Fecko, M.A. Uyar, M.U. Duale, A.Y. Amer, P.D. |
| description | We present a new model for testing real-time protocols with multiple timers, which captures complex timing dependencies by using simple linear expressions involving timer-related variables. This new modeling technique, combined with the algorithms to eliminate inconsistencies, allows generation of feasible test sequences without compromising their fault coverage. The model is specifically designed for testing to avoid performing full reachability analysis, and to control the growth of the number of test scenarios. Based on extended finite state machines, it is applicable to languages such as SDL, VHDL, and Estelle. The technique models a realistic testing framework in which each I/O exchange takes a certain time to realize and timers can be arbitrarily started or stopped. A software tool implementing this technique is used to generate test cases for the US Army wireless standard MIL-STD 188-220. |
| doi_str_mv | 10.1109/TNET.2003.818182 |
| format | Article |
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| source | IEEE Xplore |
| subjects | Associate members Automata Cities and towns Communication systems Computer programs Mathematical models Performance evaluation Protocols Reachability analysis Software Software testing Software tools System testing Timing Timing devices VHDL |
| title | A technique to generate feasible tests for communications systems with multiple timers |
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