Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques

Data dependency constraints constitute a lower bound P on the minimal clock period of single-phase clocked sequential circuits. In contrast to methods based on basic retiming, clocked sequential circuits with clock period P can always be obtained using software pipelining techniques. Such circuits c...

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Veröffentlicht in:	ACM transactions on design automation of electronic systems 2005-04, Vol.10 (2), p.187-204
Hauptverfasser:	Chabini, Noureddine, Aboulhamid, El Mostapha, Chabini, Ismaïl, Savaria, Yvon
Format:	Artikel
Sprache:	eng
Schlagworte:	Circuits Optimization Scheduling Software Studies
Online-Zugang:	Volltext
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