Performance-constrained hierarchical pipelining for behaviors, loops, and operations

Behavioral specifications of DSP systems generally contain a number of nested loops. In order to obtain high date rates for such systems, it is necessary to pipeline the system within the behavior, within the loop bodies, and also within the operations. In order to hierarchically pipeline a performa...

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Veröffentlicht in:	ACM transactions on design automation of electronic systems 2001-01, Vol.6 (1), p.1-25
Hauptverfasser:	Bakshi, Smita, Gajski, Daniel D.
Format:	Artikel
Sprache:	eng
Schlagworte:	Electronic design automation Hardware High-level and register-transfer level synthesis
Online-Zugang:	Volltext
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