A floating-gate MOS learning array with locally computed weight updates

We have demonstrated on-chip learning in an array of floating-gate MOS synapse transistors. The array comprises one synapse transistor at each node, and normalization circuitry at the row boundaries. The array computes the inner product of a column input vector and a stored weight matrix. The weight...

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Veröffentlicht in:	IEEE transactions on electron devices 1997-12, Vol.44 (12), p.2281-2289
Hauptverfasser:	Diorio, C., Hasler, P., Minch, B.A., Mead, C.A.
Format:	Artikel
Sprache:	eng
Schlagworte:	Adaptive arrays Analog computers Biology computing Circuits Concurrent computing Energy consumption Learning systems MOSFETs Physics computing Silicon
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