General-purpose systolic arrays
The extension of systolic array architecture from fixed- or special-purpose architectures to general-purpose, SIMD (single-instruction stream, multiple-data stream), MIMD (multiple-instruction stream, multiple-data stream) architectures, and hybrid architectures that combine both commercial and FPGA...
Gespeichert in:
Veröffentlicht in: | Computer (Long Beach, Calif.) Calif.), 1993-11, Vol.26 (11), p.20-31 |
---|---|
Hauptverfasser: | , , |
Format: | Artikel |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | 31 |
---|---|
container_issue | 11 |
container_start_page | 20 |
container_title | Computer (Long Beach, Calif.) |
container_volume | 26 |
creator | Johnson, K.T. Hurson, A.R. Shirazi, B. |
description | The extension of systolic array architecture from fixed- or special-purpose architectures to general-purpose, SIMD (single-instruction stream, multiple-data stream), MIMD (multiple-instruction stream, multiple-data stream) architectures, and hybrid architectures that combine both commercial and FPGA (field-programmable gate array) technologies is chronicled. The authors present a taxonomy for systolic organizations, discuss each architecture's methods of exploiting concurrencies, and compare performance attributes of each. The authors also describe a number of implementation issues that determine a systolic array's performance efficiency, such as algorithms and mapping, system integration through memory subsystems, cell granularity, and extensibility to a wide variety of topologies.< > |
doi_str_mv | 10.1109/2.241423 |
format | Article |
fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_28784700</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>241423</ieee_id><sourcerecordid>26047209</sourcerecordid><originalsourceid>FETCH-LOGICAL-c340t-789c4934cc6dc972fadd8e36622105f1ea53c47899e00b9e131dec62db5152ab3</originalsourceid><addsrcrecordid>eNqF0L1LxEAQBfBFFIynYG3jVWKz58x-JLulHOcpHNhovWw2E4jkLnE3V-S_N5LD1uoxvB9TPMZuEVaIYJ_ESihUQp6xDLU2HAyqc5YBoOEWc3HJrlL6mk5ltMzY_ZYOFH3L-2Psu0TLNKaha5uw9DH6MV2zi9q3iW5OuWCfL5uP9SvfvW_f1s87HqSCgRfGBmWlCiGvgi1E7avKkMxzIRB0jeS1DGpSlgBKSyixopCLqtSohS_lgj3Mf_vYfR8pDW7fpEBt6w_UHZMTpjCqAPgf5qAKAXaCjzMMsUspUu362Ox9HB2C-53KCTdPNdG7mTZE9MdO5Q9XQ2Gn</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>26047209</pqid></control><display><type>article</type><title>General-purpose systolic arrays</title><source>IEEE Electronic Library (IEL)</source><creator>Johnson, K.T. ; Hurson, A.R. ; Shirazi, B.</creator><creatorcontrib>Johnson, K.T. ; Hurson, A.R. ; Shirazi, B.</creatorcontrib><description>The extension of systolic array architecture from fixed- or special-purpose architectures to general-purpose, SIMD (single-instruction stream, multiple-data stream), MIMD (multiple-instruction stream, multiple-data stream) architectures, and hybrid architectures that combine both commercial and FPGA (field-programmable gate array) technologies is chronicled. The authors present a taxonomy for systolic organizations, discuss each architecture's methods of exploiting concurrencies, and compare performance attributes of each. The authors also describe a number of implementation issues that determine a systolic array's performance efficiency, such as algorithms and mapping, system integration through memory subsystems, cell granularity, and extensibility to a wide variety of topologies.< ></description><identifier>ISSN: 0018-9162</identifier><identifier>EISSN: 1558-0814</identifier><identifier>DOI: 10.1109/2.241423</identifier><identifier>CODEN: CPTRB4</identifier><language>eng</language><publisher>IEEE</publisher><subject>Computer applications ; Computer architecture ; Computer networks ; Concurrent computing ; High performance computing ; Parallel processing ; Systolic arrays ; Time sharing computer systems ; Very large scale integration ; Workstations</subject><ispartof>Computer (Long Beach, Calif.), 1993-11, Vol.26 (11), p.20-31</ispartof><lds50>peer_reviewed</lds50><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c340t-789c4934cc6dc972fadd8e36622105f1ea53c47899e00b9e131dec62db5152ab3</citedby><cites>FETCH-LOGICAL-c340t-789c4934cc6dc972fadd8e36622105f1ea53c47899e00b9e131dec62db5152ab3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/241423$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,778,782,794,27913,27914,54747</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/241423$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Johnson, K.T.</creatorcontrib><creatorcontrib>Hurson, A.R.</creatorcontrib><creatorcontrib>Shirazi, B.</creatorcontrib><title>General-purpose systolic arrays</title><title>Computer (Long Beach, Calif.)</title><addtitle>MC</addtitle><description>The extension of systolic array architecture from fixed- or special-purpose architectures to general-purpose, SIMD (single-instruction stream, multiple-data stream), MIMD (multiple-instruction stream, multiple-data stream) architectures, and hybrid architectures that combine both commercial and FPGA (field-programmable gate array) technologies is chronicled. The authors present a taxonomy for systolic organizations, discuss each architecture's methods of exploiting concurrencies, and compare performance attributes of each. The authors also describe a number of implementation issues that determine a systolic array's performance efficiency, such as algorithms and mapping, system integration through memory subsystems, cell granularity, and extensibility to a wide variety of topologies.< ></description><subject>Computer applications</subject><subject>Computer architecture</subject><subject>Computer networks</subject><subject>Concurrent computing</subject><subject>High performance computing</subject><subject>Parallel processing</subject><subject>Systolic arrays</subject><subject>Time sharing computer systems</subject><subject>Very large scale integration</subject><subject>Workstations</subject><issn>0018-9162</issn><issn>1558-0814</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1993</creationdate><recordtype>article</recordtype><recordid>eNqF0L1LxEAQBfBFFIynYG3jVWKz58x-JLulHOcpHNhovWw2E4jkLnE3V-S_N5LD1uoxvB9TPMZuEVaIYJ_ESihUQp6xDLU2HAyqc5YBoOEWc3HJrlL6mk5ltMzY_ZYOFH3L-2Psu0TLNKaha5uw9DH6MV2zi9q3iW5OuWCfL5uP9SvfvW_f1s87HqSCgRfGBmWlCiGvgi1E7avKkMxzIRB0jeS1DGpSlgBKSyixopCLqtSohS_lgj3Mf_vYfR8pDW7fpEBt6w_UHZMTpjCqAPgf5qAKAXaCjzMMsUspUu362Ox9HB2C-53KCTdPNdG7mTZE9MdO5Q9XQ2Gn</recordid><startdate>19931101</startdate><enddate>19931101</enddate><creator>Johnson, K.T.</creator><creator>Hurson, A.R.</creator><creator>Shirazi, B.</creator><general>IEEE</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>8FD</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope><scope>7SP</scope></search><sort><creationdate>19931101</creationdate><title>General-purpose systolic arrays</title><author>Johnson, K.T. ; Hurson, A.R. ; Shirazi, B.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c340t-789c4934cc6dc972fadd8e36622105f1ea53c47899e00b9e131dec62db5152ab3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1993</creationdate><topic>Computer applications</topic><topic>Computer architecture</topic><topic>Computer networks</topic><topic>Concurrent computing</topic><topic>High performance computing</topic><topic>Parallel processing</topic><topic>Systolic arrays</topic><topic>Time sharing computer systems</topic><topic>Very large scale integration</topic><topic>Workstations</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Johnson, K.T.</creatorcontrib><creatorcontrib>Hurson, A.R.</creatorcontrib><creatorcontrib>Shirazi, B.</creatorcontrib><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Technology Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><collection>Electronics & Communications Abstracts</collection><jtitle>Computer (Long Beach, Calif.)</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Johnson, K.T.</au><au>Hurson, A.R.</au><au>Shirazi, B.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>General-purpose systolic arrays</atitle><jtitle>Computer (Long Beach, Calif.)</jtitle><stitle>MC</stitle><date>1993-11-01</date><risdate>1993</risdate><volume>26</volume><issue>11</issue><spage>20</spage><epage>31</epage><pages>20-31</pages><issn>0018-9162</issn><eissn>1558-0814</eissn><coden>CPTRB4</coden><abstract>The extension of systolic array architecture from fixed- or special-purpose architectures to general-purpose, SIMD (single-instruction stream, multiple-data stream), MIMD (multiple-instruction stream, multiple-data stream) architectures, and hybrid architectures that combine both commercial and FPGA (field-programmable gate array) technologies is chronicled. The authors present a taxonomy for systolic organizations, discuss each architecture's methods of exploiting concurrencies, and compare performance attributes of each. The authors also describe a number of implementation issues that determine a systolic array's performance efficiency, such as algorithms and mapping, system integration through memory subsystems, cell granularity, and extensibility to a wide variety of topologies.< ></abstract><pub>IEEE</pub><doi>10.1109/2.241423</doi><tpages>12</tpages><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | ISSN: 0018-9162 |
ispartof | Computer (Long Beach, Calif.), 1993-11, Vol.26 (11), p.20-31 |
issn | 0018-9162 1558-0814 |
language | eng |
recordid | cdi_proquest_miscellaneous_28784700 |
source | IEEE Electronic Library (IEL) |
subjects | Computer applications Computer architecture Computer networks Concurrent computing High performance computing Parallel processing Systolic arrays Time sharing computer systems Very large scale integration Workstations |
title | General-purpose systolic arrays |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-15T09%3A08%3A37IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=General-purpose%20systolic%20arrays&rft.jtitle=Computer%20(Long%20Beach,%20Calif.)&rft.au=Johnson,%20K.T.&rft.date=1993-11-01&rft.volume=26&rft.issue=11&rft.spage=20&rft.epage=31&rft.pages=20-31&rft.issn=0018-9162&rft.eissn=1558-0814&rft.coden=CPTRB4&rft_id=info:doi/10.1109/2.241423&rft_dat=%3Cproquest_RIE%3E26047209%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=26047209&rft_id=info:pmid/&rft_ieee_id=241423&rfr_iscdi=true |