Experimental investigation of the impact of LWR on sub-100-nm device performance
Argon Fluoride (ArF) lithography is essential to develop a sub-100-nm device, however, line edge roughness (LER) and line width roughness (LWR) is playing a critical role due to the immaturity of photoresist and the lack of etch resistance. Researchers are trying to improve LER and LWR properties by...
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| Veröffentlicht in: | IEEE transactions on electron devices 2004-12, Vol.51 (12), p.1984-1988 |
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| container_end_page | 1988 |
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| container_issue | 12 |
| container_start_page | 1984 |
| container_title | IEEE transactions on electron devices |
| container_volume | 51 |
| creator | Hyun-Woo Kim Ji-Young Lee Shin, J. Sang-Gyun Woo Han-Ku Cho Joo-Tae Moon |
| description | Argon Fluoride (ArF) lithography is essential to develop a sub-100-nm device, however, line edge roughness (LER) and line width roughness (LWR) is playing a critical role due to the immaturity of photoresist and the lack of etch resistance. Researchers are trying to improve LER and LWR properties by optimizing photoresist materials and process conditions. In this paper, experiment results are presented to study the impact of LER and LWR to device performance so that the reasonable control range of LER and LWR can be defined. To implement the experiment, a 80-nm node of single negative-channel metal-oxide-semiconductor transistors were fabricated, which had various ranges of gate length, width, LER, and LWR. The amount of LER and LWR could be successfully controlled by applying different resist materials, defocus, and overetch time. Experimental results show that leakage current is significantly increased as LWR increases when the gate length is less than 85 nm. The main degradation is standard deviation of off-current (I/sub off/), and LWR is better representation to characterize a device performance. |
| doi_str_mv | 10.1109/TED.2004.839115 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_28755540</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1362957</ieee_id><sourcerecordid>2428102291</sourcerecordid><originalsourceid>FETCH-LOGICAL-c446t-851b84119ca996fea36925ead762db1553864068471abae3c41a48255c7796f33</originalsourceid><addsrcrecordid>eNqFkctLAzEQxoMoWKtnD14WQW_bZjaPTY5S6wMKilQ8hjSd1ZR91M226H9vagsFL56Gmfzm48t8hJwDHQBQPZyObwcZpXygmAYQB6QHQuSpllwekh6loFLNFDsmJyEsYis5z3rkefy1xNZXWHe2THy9xtD5d9v5pk6aIuk-MPHV0rpu003eXpI4D6tZCpSmdZXMce0dJlGiaNrK1g5PyVFhy4Bnu9onr3fj6eghnTzdP45uJqnjXHapEjBTHEA7q7Us0DKpM4F2nstsPovOmZKcSsVzsDOLzHGwXGVCuDyPPGN9cr3VXbbN5yq6NpUPDsvS1tisgsk0VQpA_g-qXAjBaQQv_4CLZtXW8RNGRatU81-14RZybRNCi4VZxuvZ9tsANZscTMzBbHIw2xzixtVO1gZny6KNV_JhvyYzJZiEyF1sOY-I-2cmMy1y9gNegY3R</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>884109416</pqid></control><display><type>article</type><title>Experimental investigation of the impact of LWR on sub-100-nm device performance</title><source>IEEE</source><creator>Hyun-Woo Kim ; Ji-Young Lee ; Shin, J. ; Sang-Gyun Woo ; Han-Ku Cho ; Joo-Tae Moon</creator><creatorcontrib>Hyun-Woo Kim ; Ji-Young Lee ; Shin, J. ; Sang-Gyun Woo ; Han-Ku Cho ; Joo-Tae Moon</creatorcontrib><description>Argon Fluoride (ArF) lithography is essential to develop a sub-100-nm device, however, line edge roughness (LER) and line width roughness (LWR) is playing a critical role due to the immaturity of photoresist and the lack of etch resistance. Researchers are trying to improve LER and LWR properties by optimizing photoresist materials and process conditions. In this paper, experiment results are presented to study the impact of LER and LWR to device performance so that the reasonable control range of LER and LWR can be defined. To implement the experiment, a 80-nm node of single negative-channel metal-oxide-semiconductor transistors were fabricated, which had various ranges of gate length, width, LER, and LWR. The amount of LER and LWR could be successfully controlled by applying different resist materials, defocus, and overetch time. Experimental results show that leakage current is significantly increased as LWR increases when the gate length is less than 85 nm. The main degradation is standard deviation of off-current (I/sub off/), and LWR is better representation to characterize a device performance.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/TED.2004.839115</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Argon materials/devices ; Electronics ; Exact sciences and technology ; Line edge roughness (LER) ; line width roughness (LWR) ; Lithography ; Microelectronic fabrication (materials and surfaces technology) ; MOSFETs ; Nanotechnology ; nMOS ; Resists ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Standard deviation ; Transistors</subject><ispartof>IEEE transactions on electron devices, 2004-12, Vol.51 (12), p.1984-1988</ispartof><rights>2005 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2004</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c446t-851b84119ca996fea36925ead762db1553864068471abae3c41a48255c7796f33</citedby><cites>FETCH-LOGICAL-c446t-851b84119ca996fea36925ead762db1553864068471abae3c41a48255c7796f33</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1362957$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>315,781,785,797,27928,27929,54762</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1362957$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=16285361$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Hyun-Woo Kim</creatorcontrib><creatorcontrib>Ji-Young Lee</creatorcontrib><creatorcontrib>Shin, J.</creatorcontrib><creatorcontrib>Sang-Gyun Woo</creatorcontrib><creatorcontrib>Han-Ku Cho</creatorcontrib><creatorcontrib>Joo-Tae Moon</creatorcontrib><title>Experimental investigation of the impact of LWR on sub-100-nm device performance</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>Argon Fluoride (ArF) lithography is essential to develop a sub-100-nm device, however, line edge roughness (LER) and line width roughness (LWR) is playing a critical role due to the immaturity of photoresist and the lack of etch resistance. Researchers are trying to improve LER and LWR properties by optimizing photoresist materials and process conditions. In this paper, experiment results are presented to study the impact of LER and LWR to device performance so that the reasonable control range of LER and LWR can be defined. To implement the experiment, a 80-nm node of single negative-channel metal-oxide-semiconductor transistors were fabricated, which had various ranges of gate length, width, LER, and LWR. The amount of LER and LWR could be successfully controlled by applying different resist materials, defocus, and overetch time. Experimental results show that leakage current is significantly increased as LWR increases when the gate length is less than 85 nm. The main degradation is standard deviation of off-current (I/sub off/), and LWR is better representation to characterize a device performance.</description><subject>Applied sciences</subject><subject>Argon materials/devices</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Line edge roughness (LER)</subject><subject>line width roughness (LWR)</subject><subject>Lithography</subject><subject>Microelectronic fabrication (materials and surfaces technology)</subject><subject>MOSFETs</subject><subject>Nanotechnology</subject><subject>nMOS</subject><subject>Resists</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Standard deviation</subject><subject>Transistors</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2004</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqFkctLAzEQxoMoWKtnD14WQW_bZjaPTY5S6wMKilQ8hjSd1ZR91M226H9vagsFL56Gmfzm48t8hJwDHQBQPZyObwcZpXygmAYQB6QHQuSpllwekh6loFLNFDsmJyEsYis5z3rkefy1xNZXWHe2THy9xtD5d9v5pk6aIuk-MPHV0rpu003eXpI4D6tZCpSmdZXMce0dJlGiaNrK1g5PyVFhy4Bnu9onr3fj6eghnTzdP45uJqnjXHapEjBTHEA7q7Us0DKpM4F2nstsPovOmZKcSsVzsDOLzHGwXGVCuDyPPGN9cr3VXbbN5yq6NpUPDsvS1tisgsk0VQpA_g-qXAjBaQQv_4CLZtXW8RNGRatU81-14RZybRNCi4VZxuvZ9tsANZscTMzBbHIw2xzixtVO1gZny6KNV_JhvyYzJZiEyF1sOY-I-2cmMy1y9gNegY3R</recordid><startdate>20041201</startdate><enddate>20041201</enddate><creator>Hyun-Woo Kim</creator><creator>Ji-Young Lee</creator><creator>Shin, J.</creator><creator>Sang-Gyun Woo</creator><creator>Han-Ku Cho</creator><creator>Joo-Tae Moon</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>7U5</scope></search><sort><creationdate>20041201</creationdate><title>Experimental investigation of the impact of LWR on sub-100-nm device performance</title><author>Hyun-Woo Kim ; Ji-Young Lee ; Shin, J. ; Sang-Gyun Woo ; Han-Ku Cho ; Joo-Tae Moon</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c446t-851b84119ca996fea36925ead762db1553864068471abae3c41a48255c7796f33</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Applied sciences</topic><topic>Argon materials/devices</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Line edge roughness (LER)</topic><topic>line width roughness (LWR)</topic><topic>Lithography</topic><topic>Microelectronic fabrication (materials and surfaces technology)</topic><topic>MOSFETs</topic><topic>Nanotechnology</topic><topic>nMOS</topic><topic>Resists</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Standard deviation</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Hyun-Woo Kim</creatorcontrib><creatorcontrib>Ji-Young Lee</creatorcontrib><creatorcontrib>Shin, J.</creatorcontrib><creatorcontrib>Sang-Gyun Woo</creatorcontrib><creatorcontrib>Han-Ku Cho</creatorcontrib><creatorcontrib>Joo-Tae Moon</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) Online</collection><collection>IEEE</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Solid State and Superconductivity Abstracts</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hyun-Woo Kim</au><au>Ji-Young Lee</au><au>Shin, J.</au><au>Sang-Gyun Woo</au><au>Han-Ku Cho</au><au>Joo-Tae Moon</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Experimental investigation of the impact of LWR on sub-100-nm device performance</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>2004-12-01</date><risdate>2004</risdate><volume>51</volume><issue>12</issue><spage>1984</spage><epage>1988</epage><pages>1984-1988</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>Argon Fluoride (ArF) lithography is essential to develop a sub-100-nm device, however, line edge roughness (LER) and line width roughness (LWR) is playing a critical role due to the immaturity of photoresist and the lack of etch resistance. Researchers are trying to improve LER and LWR properties by optimizing photoresist materials and process conditions. In this paper, experiment results are presented to study the impact of LER and LWR to device performance so that the reasonable control range of LER and LWR can be defined. To implement the experiment, a 80-nm node of single negative-channel metal-oxide-semiconductor transistors were fabricated, which had various ranges of gate length, width, LER, and LWR. The amount of LER and LWR could be successfully controlled by applying different resist materials, defocus, and overetch time. Experimental results show that leakage current is significantly increased as LWR increases when the gate length is less than 85 nm. The main degradation is standard deviation of off-current (I/sub off/), and LWR is better representation to characterize a device performance.</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/TED.2004.839115</doi><tpages>5</tpages></addata></record> |
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| language | eng |
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| subjects | Applied sciences Argon materials/devices Electronics Exact sciences and technology Line edge roughness (LER) line width roughness (LWR) Lithography Microelectronic fabrication (materials and surfaces technology) MOSFETs Nanotechnology nMOS Resists Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Standard deviation Transistors |
| title | Experimental investigation of the impact of LWR on sub-100-nm device performance |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-17T13%3A41%3A51IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Experimental%20investigation%20of%20the%20impact%20of%20LWR%20on%20sub-100-nm%20device%20performance&rft.jtitle=IEEE%20transactions%20on%20electron%20devices&rft.au=Hyun-Woo%20Kim&rft.date=2004-12-01&rft.volume=51&rft.issue=12&rft.spage=1984&rft.epage=1988&rft.pages=1984-1988&rft.issn=0018-9383&rft.eissn=1557-9646&rft.coden=IETDAI&rft_id=info:doi/10.1109/TED.2004.839115&rft_dat=%3Cproquest_RIE%3E2428102291%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=884109416&rft_id=info:pmid/&rft_ieee_id=1362957&rfr_iscdi=true |