Automated low-power technique exploiting multiple supply voltages applied to a media processor
This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement, and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The p...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 1998-03, Vol.33 (3), p.463-472 |
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| container_end_page | 472 |
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| container_issue | 3 |
| container_start_page | 463 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 33 |
| creator | Usami, K. Igarashi, M. Minami, F. Ishikawa, T. Kanzawa, M. Ichida, M. Nogami, K. |
| description | This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement, and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. The reduced supply, voltage is also exploited in a clock tree to reduce power. Combining these techniques together, we applied it to a media processor chip. The combined technique reduced the power by 47% in random-logic modules and by 73% in the clock tree, while keeping the performance. |
| doi_str_mv | 10.1109/4.661212 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_28720462</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>661212</ieee_id><sourcerecordid>28720462</sourcerecordid><originalsourceid>FETCH-LOGICAL-c341t-fe1d14fe9e255dfdc8a75ddf6dda988807539a5da1915173b59de8850feec2d83</originalsourceid><addsrcrecordid>eNo9kM1LxDAQxYMouK6CZ085iZeumbRp0-Oy-AWCFwVPlthM10i6qUnquv-9kS6ehsf8ZubNI-Qc2AKA1dfFoiyBAz8gMxBCZlDlr4dkxhjIrOaMHZOTED6TLAoJM_K2HKPrVURNrdtmg9uipxHbj435GpHiz2CdiWazpv1ooxks0jAOg93Rb2ejWmOgKkmT5qOjivaojaKDdy2G4PwpOeqUDXi2r3PycnvzvLrPHp_uHlbLx6zNC4hZh6Ch6LBGLoTudCtVJbTuSq1VLaVklchrJbSCGkT66F3UGqUUrENsuZb5nFxOe9Pl5DvEpjehRWvVBt0YGi4rzoqSJ_BqAlvvQvDYNYM3vfK7BljzF2BTNFOACb2YUIOI_9i--QssA22Q</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>28720462</pqid></control><display><type>article</type><title>Automated low-power technique exploiting multiple supply voltages applied to a media processor</title><source>IEEE Electronic Library (IEL)</source><creator>Usami, K. ; Igarashi, M. ; Minami, F. ; Ishikawa, T. ; Kanzawa, M. ; Ichida, M. ; Nogami, K.</creator><creatorcontrib>Usami, K. ; Igarashi, M. ; Minami, F. ; Ishikawa, T. ; Kanzawa, M. ; Ichida, M. ; Nogami, K.</creatorcontrib><description>This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement, and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. The reduced supply, voltage is also exploited in a clock tree to reduce power. Combining these techniques together, we applied it to a media processor chip. The combined technique reduced the power by 47% in random-logic modules and by 73% in the clock tree, while keeping the performance.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.661212</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>IEEE</publisher><subject>Circuit synthesis ; Clocks ; Degradation ; Delay ; Design automation ; Leakage current ; Logic circuits ; Routing ; Timing ; Voltage</subject><ispartof>IEEE journal of solid-state circuits, 1998-03, Vol.33 (3), p.463-472</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c341t-fe1d14fe9e255dfdc8a75ddf6dda988807539a5da1915173b59de8850feec2d83</citedby><cites>FETCH-LOGICAL-c341t-fe1d14fe9e255dfdc8a75ddf6dda988807539a5da1915173b59de8850feec2d83</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/661212$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,777,781,793,27905,27906,54739</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/661212$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Usami, K.</creatorcontrib><creatorcontrib>Igarashi, M.</creatorcontrib><creatorcontrib>Minami, F.</creatorcontrib><creatorcontrib>Ishikawa, T.</creatorcontrib><creatorcontrib>Kanzawa, M.</creatorcontrib><creatorcontrib>Ichida, M.</creatorcontrib><creatorcontrib>Nogami, K.</creatorcontrib><title>Automated low-power technique exploiting multiple supply voltages applied to a media processor</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement, and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. The reduced supply, voltage is also exploited in a clock tree to reduce power. Combining these techniques together, we applied it to a media processor chip. The combined technique reduced the power by 47% in random-logic modules and by 73% in the clock tree, while keeping the performance.</description><subject>Circuit synthesis</subject><subject>Clocks</subject><subject>Degradation</subject><subject>Delay</subject><subject>Design automation</subject><subject>Leakage current</subject><subject>Logic circuits</subject><subject>Routing</subject><subject>Timing</subject><subject>Voltage</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1998</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNo9kM1LxDAQxYMouK6CZ085iZeumbRp0-Oy-AWCFwVPlthM10i6qUnquv-9kS6ehsf8ZubNI-Qc2AKA1dfFoiyBAz8gMxBCZlDlr4dkxhjIrOaMHZOTED6TLAoJM_K2HKPrVURNrdtmg9uipxHbj435GpHiz2CdiWazpv1ooxks0jAOg93Rb2ejWmOgKkmT5qOjivaojaKDdy2G4PwpOeqUDXi2r3PycnvzvLrPHp_uHlbLx6zNC4hZh6Ch6LBGLoTudCtVJbTuSq1VLaVklchrJbSCGkT66F3UGqUUrENsuZb5nFxOe9Pl5DvEpjehRWvVBt0YGi4rzoqSJ_BqAlvvQvDYNYM3vfK7BljzF2BTNFOACb2YUIOI_9i--QssA22Q</recordid><startdate>199803</startdate><enddate>199803</enddate><creator>Usami, K.</creator><creator>Igarashi, M.</creator><creator>Minami, F.</creator><creator>Ishikawa, T.</creator><creator>Kanzawa, M.</creator><creator>Ichida, M.</creator><creator>Nogami, K.</creator><general>IEEE</general><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>199803</creationdate><title>Automated low-power technique exploiting multiple supply voltages applied to a media processor</title><author>Usami, K. ; Igarashi, M. ; Minami, F. ; Ishikawa, T. ; Kanzawa, M. ; Ichida, M. ; Nogami, K.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c341t-fe1d14fe9e255dfdc8a75ddf6dda988807539a5da1915173b59de8850feec2d83</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1998</creationdate><topic>Circuit synthesis</topic><topic>Clocks</topic><topic>Degradation</topic><topic>Delay</topic><topic>Design automation</topic><topic>Leakage current</topic><topic>Logic circuits</topic><topic>Routing</topic><topic>Timing</topic><topic>Voltage</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Usami, K.</creatorcontrib><creatorcontrib>Igarashi, M.</creatorcontrib><creatorcontrib>Minami, F.</creatorcontrib><creatorcontrib>Ishikawa, T.</creatorcontrib><creatorcontrib>Kanzawa, M.</creatorcontrib><creatorcontrib>Ichida, M.</creatorcontrib><creatorcontrib>Nogami, K.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Usami, K.</au><au>Igarashi, M.</au><au>Minami, F.</au><au>Ishikawa, T.</au><au>Kanzawa, M.</au><au>Ichida, M.</au><au>Nogami, K.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Automated low-power technique exploiting multiple supply voltages applied to a media processor</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1998-03</date><risdate>1998</risdate><volume>33</volume><issue>3</issue><spage>463</spage><epage>472</epage><pages>463-472</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>This paper describes an automated design technique to reduce power by making use of two supply voltages. The technique consists of structure synthesis, placement, and routing. The structure synthesizer clusters the gates off the critical paths so as to supply the reduced voltage to save power. The placement and routing tool assigns either the reduced voltage or the unreduced one to each row so as to minimize the area overhead. The reduced supply, voltage is also exploited in a clock tree to reduce power. Combining these techniques together, we applied it to a media processor chip. The combined technique reduced the power by 47% in random-logic modules and by 73% in the clock tree, while keeping the performance.</abstract><pub>IEEE</pub><doi>10.1109/4.661212</doi><tpages>10</tpages></addata></record> |
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| ispartof | IEEE journal of solid-state circuits, 1998-03, Vol.33 (3), p.463-472 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_proquest_miscellaneous_28720462 |
| source | IEEE Electronic Library (IEL) |
| subjects | Circuit synthesis Clocks Degradation Delay Design automation Leakage current Logic circuits Routing Timing Voltage |
| title | Automated low-power technique exploiting multiple supply voltages applied to a media processor |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-18T12%3A43%3A32IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Automated%20low-power%20technique%20exploiting%20multiple%20supply%20voltages%20applied%20to%20a%20media%20processor&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Usami,%20K.&rft.date=1998-03&rft.volume=33&rft.issue=3&rft.spage=463&rft.epage=472&rft.pages=463-472&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/4.661212&rft_dat=%3Cproquest_RIE%3E28720462%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=28720462&rft_id=info:pmid/&rft_ieee_id=661212&rfr_iscdi=true |