Exact and Approximate Solutions for the Gate Matrix Layout Problem
We consider the gate matrix layout problem for VLSI circuits, which is known to be NP-complete. We present an efficient algorithm for determining whether two tracks suffice. For the general problem of minimizing the number of tracks (and, hence, the area) needed, we design an attractive dynamic prog...
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| Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 1987-01, Vol.6 (1), p.79-84 |
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| container_end_page | 84 |
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| container_title | IEEE transactions on computer-aided design of integrated circuits and systems |
| container_volume | 6 |
| creator | Deo, N. Krishnamoorthy, M.S. Langston, M.A. |
| description | We consider the gate matrix layout problem for VLSI circuits, which is known to be NP-complete. We present an efficient algorithm for determining whether two tracks suffice. For the general problem of minimizing the number of tracks (and, hence, the area) needed, we design an attractive dynamic programming formulation to guarantee optimality. We also investigate the performance of fast heuristic algorithms published in the literature and demonstrate that there exist families of problem instances for which the ratio of the number of tracks required by these heuristics to the optimal value is unbounded. Moreover, we show that this result holds for any on-line layout algorithm. We additionally prove that, unless P = NP, no polynomial-time layout algorithm can ensure that the number of tracks it requires never exceeds k plus the optimum, for any constant k. |
| doi_str_mv | 10.1109/TCAD.1987.1270248 |
| format | Article |
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We present an efficient algorithm for determining whether two tracks suffice. For the general problem of minimizing the number of tracks (and, hence, the area) needed, we design an attractive dynamic programming formulation to guarantee optimality. We also investigate the performance of fast heuristic algorithms published in the literature and demonstrate that there exist families of problem instances for which the ratio of the number of tracks required by these heuristics to the optimal value is unbounded. Moreover, we show that this result holds for any on-line layout algorithm. We additionally prove that, unless P = NP, no polynomial-time layout algorithm can ensure that the number of tracks it requires never exceeds k plus the optimum, for any constant k.</description><identifier>ISSN: 0278-0070</identifier><identifier>EISSN: 1937-4151</identifier><identifier>DOI: 10.1109/TCAD.1987.1270248</identifier><identifier>CODEN: ITCSDI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Computer science ; Design automation ; Dynamic programming ; Electronics ; Exact sciences and technology ; Heuristic algorithms ; Integrated circuit interconnections ; Integrated circuits ; Semiconductor electronics. Microelectronics. Optoelectronics. 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We present an efficient algorithm for determining whether two tracks suffice. For the general problem of minimizing the number of tracks (and, hence, the area) needed, we design an attractive dynamic programming formulation to guarantee optimality. We also investigate the performance of fast heuristic algorithms published in the literature and demonstrate that there exist families of problem instances for which the ratio of the number of tracks required by these heuristics to the optimal value is unbounded. Moreover, we show that this result holds for any on-line layout algorithm. We additionally prove that, unless P = NP, no polynomial-time layout algorithm can ensure that the number of tracks it requires never exceeds k plus the optimum, for any constant k.</description><subject>Applied sciences</subject><subject>Computer science</subject><subject>Design automation</subject><subject>Dynamic programming</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Heuristic algorithms</subject><subject>Integrated circuit interconnections</subject><subject>Integrated circuits</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Microelectronics. Optoelectronics. Solid state devices</topic><topic>Silicon</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Deo, N.</creatorcontrib><creatorcontrib>Krishnamoorthy, M.S.</creatorcontrib><creatorcontrib>Langston, M.A.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics & Communications Abstracts</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Technology Research Database</collection><collection>Engineering Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Deo, N.</au><au>Krishnamoorthy, M.S.</au><au>Langston, M.A.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Exact and Approximate Solutions for the Gate Matrix Layout Problem</atitle><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle><stitle>TCAD</stitle><date>1987-01</date><risdate>1987</risdate><volume>6</volume><issue>1</issue><spage>79</spage><epage>84</epage><pages>79-84</pages><issn>0278-0070</issn><eissn>1937-4151</eissn><coden>ITCSDI</coden><abstract>We consider the gate matrix layout problem for VLSI circuits, which is known to be NP-complete. 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| identifier | ISSN: 0278-0070 |
| ispartof | IEEE transactions on computer-aided design of integrated circuits and systems, 1987-01, Vol.6 (1), p.79-84 |
| issn | 0278-0070 1937-4151 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Computer science Design automation Dynamic programming Electronics Exact sciences and technology Heuristic algorithms Integrated circuit interconnections Integrated circuits Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Silicon Very large scale integration |
| title | Exact and Approximate Solutions for the Gate Matrix Layout Problem |
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