A VME 32 channel pipeline TDC module with TMC LSIs
A new 32-channel pipeline TDC module, which implements custom-developed time memory cell LSIs, has been developed for high-rate wire-chamber applications. The module has achieved a 370 ps time resolution, and records data for a period of 3.2 /spl mu/sec. To handle the large data size, a digital sign...
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Veröffentlicht in: | IEEE Transactions on Nuclear Science 1996-06, Vol.43 (3), p.1799-1803 |
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container_title | IEEE Transactions on Nuclear Science |
container_volume | 43 |
creator | Shirasu, H. Arai, Y. Ikeno, M. Murata, T. Emura, T. |
description | A new 32-channel pipeline TDC module, which implements custom-developed time memory cell LSIs, has been developed for high-rate wire-chamber applications. The module has achieved a 370 ps time resolution, and records data for a period of 3.2 /spl mu/sec. To handle the large data size, a digital signal processor (DSP56002) is implemented in the module. Most of the control logic is implemented in two complex PLDs to achieve a density of 32 channels in a single-width; double-height VME module. |
doi_str_mv | 10.1109/23.507225 |
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Most of the control logic is implemented in two complex PLDs to achieve a density of 32 channels in a single-width; double-height VME module.</description><subject>ANALOG-TO-DIGITAL CONVERTERS</subject><subject>Clocks</subject><subject>CMOS technology</subject><subject>Costs</subject><subject>DATA ACQUISITION SYSTEMS</subject><subject>DATA TRANSMISSION</subject><subject>Digital signal processing chips</subject><subject>Digital signal processors</subject><subject>ELECTRONIC CIRCUITS</subject><subject>Frequency</subject><subject>INSTRUMENTATION, INCLUDING NUCLEAR AND PARTICLE DETECTORS</subject><subject>Large scale integration</subject><subject>Pipelines</subject><subject>READOUT SYSTEMS</subject><subject>Signal resolution</subject><subject>Timing</subject><subject>TIMING CIRCUITS</subject><subject>WIRE SPARK CHAMBERS</subject><issn>0018-9499</issn><issn>1558-1578</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1996</creationdate><recordtype>article</recordtype><recordid>eNo90MFLwzAUBvAgCs7pwauneBE8dCZ5TdIcR5062PDg9Bqy9JVFurY2HeJ_b6XD0-Pxfnw8PkKuOZtxzsyDgJlkWgh5QiZcyizhUmenZMIYzxKTGnNOLmL8HNZUMjkhYk4_1gsKgvqdq2usaBtarEKNdPOY031THCqk36Hf0c06p6u3ZbwkZ6WrIl4d55S8Py02-Uuyen1e5vNV4oFBnxRbbiSIotQamETOMu0kOm6MSDXnKNMC0kIAbg2iVFxp4QzAFkFAyZiGKbkdc5vYBxt96NHvfDM86XsrtJIMBnM3mrZrvg4Ye7sP0WNVuRqbQ7QiUwqUSgd4P0LfNTF2WNq2C3vX_VjO7F9zVoAdmxvszWgDIv674_EX6ZtjZw</recordid><startdate>19960601</startdate><enddate>19960601</enddate><creator>Shirasu, H.</creator><creator>Arai, Y.</creator><creator>Ikeno, M.</creator><creator>Murata, T.</creator><creator>Emura, T.</creator><general>IEEE</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope><scope>OTOTI</scope></search><sort><creationdate>19960601</creationdate><title>A VME 32 channel pipeline TDC module with TMC LSIs</title><author>Shirasu, H. ; Arai, Y. ; Ikeno, M. ; Murata, T. ; Emura, T.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c303t-db19532df77305e1087a5ea19924711e54d34d23eb9ee561672a933be323f0073</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1996</creationdate><topic>ANALOG-TO-DIGITAL CONVERTERS</topic><topic>Clocks</topic><topic>CMOS technology</topic><topic>Costs</topic><topic>DATA ACQUISITION SYSTEMS</topic><topic>DATA TRANSMISSION</topic><topic>Digital signal processing chips</topic><topic>Digital signal processors</topic><topic>ELECTRONIC CIRCUITS</topic><topic>Frequency</topic><topic>INSTRUMENTATION, INCLUDING NUCLEAR AND PARTICLE DETECTORS</topic><topic>Large scale integration</topic><topic>Pipelines</topic><topic>READOUT SYSTEMS</topic><topic>Signal resolution</topic><topic>Timing</topic><topic>TIMING CIRCUITS</topic><topic>WIRE SPARK CHAMBERS</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Shirasu, H.</creatorcontrib><creatorcontrib>Arai, Y.</creatorcontrib><creatorcontrib>Ikeno, M.</creatorcontrib><creatorcontrib>Murata, T.</creatorcontrib><creatorcontrib>Emura, T.</creatorcontrib><collection>CrossRef</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>OSTI.GOV</collection><jtitle>IEEE Transactions on Nuclear Science</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Shirasu, H.</au><au>Arai, Y.</au><au>Ikeno, M.</au><au>Murata, T.</au><au>Emura, T.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A VME 32 channel pipeline TDC module with TMC LSIs</atitle><jtitle>IEEE Transactions on Nuclear Science</jtitle><stitle>TNS</stitle><date>1996-06-01</date><risdate>1996</risdate><volume>43</volume><issue>3</issue><spage>1799</spage><epage>1803</epage><pages>1799-1803</pages><issn>0018-9499</issn><eissn>1558-1578</eissn><coden>IETNAE</coden><abstract>A new 32-channel pipeline TDC module, which implements custom-developed time memory cell LSIs, has been developed for high-rate wire-chamber applications. The module has achieved a 370 ps time resolution, and records data for a period of 3.2 /spl mu/sec. To handle the large data size, a digital signal processor (DSP56002) is implemented in the module. Most of the control logic is implemented in two complex PLDs to achieve a density of 32 channels in a single-width; double-height VME module.</abstract><cop>United States</cop><pub>IEEE</pub><doi>10.1109/23.507225</doi><tpages>5</tpages></addata></record> |
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subjects | ANALOG-TO-DIGITAL CONVERTERS Clocks CMOS technology Costs DATA ACQUISITION SYSTEMS DATA TRANSMISSION Digital signal processing chips Digital signal processors ELECTRONIC CIRCUITS Frequency INSTRUMENTATION, INCLUDING NUCLEAR AND PARTICLE DETECTORS Large scale integration Pipelines READOUT SYSTEMS Signal resolution Timing TIMING CIRCUITS WIRE SPARK CHAMBERS |
title | A VME 32 channel pipeline TDC module with TMC LSIs |
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