The impact of intra-die device parameter variations on path delays and on the design for yield of low voltage digital circuits

The yield of low voltage digital circuits is found to he sensitive to local gate delay variations due to uncorrelated intra-die parameter deviations. Caused by statistical deviations of the doping concentration they lead to more pronounced delay variations for minimum transistor sizes. Their influen...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 1997-12, Vol.5 (4), p.360-368
Hauptverfasser:	Eisele, M., Berthold, J., Schmitt-Landsiedel, D., Mahnkopf, R.
Format:	Artikel
Sprache:	eng
Schlagworte:	Adders Applied sciences Circuit testing CMOS digital integrated circuits CMOS logic circuits CMOS technology Delay Design. Technologies. Operation analysis. Testing Digital circuits Doping Electronics Exact sciences and technology Integrated circuits Low voltage Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Threshold voltage
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