Single event effects in PDSOI 4 M SRAM fabricated in UNIBOND

Heavy ion and proton single event upsets of 4 M SOI SRAM with a hardened delay element in each memory cell were evaluated. These 4 M SRAM were fabricated in UNIBOND substrates using a radiation hardened partially depleted silicon-on-insulator CMOS technology. Limiting heavy ion upset cross-section o...

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Veröffentlicht in:	IEEE transactions on nuclear science 2003-12, Vol.50 (6), p.2095-2100
Hauptverfasser:	Liu, S.T., Heikkila, W.W., Golke, K.W., Anthony, D., Hurst, A., Kirchner, G., Jenkins, W.C., Hughes, H.L., Mitra, S., Ioannou, D.E.
Format:	Artikel
Sprache:	eng
Schlagworte:	CMOS CMOS technology Constraining Cross sections Delay Depletion Dielectric substrates Energy measurement Laboratories Protons Radiation hardening Random access memory Silicon on insulator technology Single Event Effects Single event upset Single event upsets Static random access memory
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Beschreibung
Zusammenfassung:	Heavy ion and proton single event upsets of 4 M SOI SRAM with a hardened delay element in each memory cell were evaluated. These 4 M SRAM were fabricated in UNIBOND substrates using a radiation hardened partially depleted silicon-on-insulator CMOS technology. Limiting heavy ion upset cross-section of 1.2/spl times/10/sup -10/ cm/sup 2//bit has been achieved. Limiting proton upset cross-section of 1.1/spl times/10/sup -17/ cm/sup 2//bit has also been obtained.
ISSN:	0018-9499 1558-1578
DOI:	10.1109/TNS.2003.821832