Stacked modular package
This paper reports on a vertical package developed to enable size reduction of electronics for miniaturized products. The features of portable and handheld devices have increased whereas size is continually reduced. System-on-a-chip is the most effective size reduction approach, but is not a good bu...
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| Veröffentlicht in: | IEEE transactions on advanced packaging 2004-08, Vol.27 (3), p.461-466 |
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| container_title | IEEE transactions on advanced packaging |
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| creator | Pienimaa, S.K. Miettinen, J. Ristolainen, E. |
| description | This paper reports on a vertical package developed to enable size reduction of electronics for miniaturized products. The features of portable and handheld devices have increased whereas size is continually reduced. System-on-a-chip is the most effective size reduction approach, but is not a good business when excessively complex and oversized low yielding chips are required. A vertical package is a cost-effective solution to save placement and routing area on the board. Furthermore, a vertical module enables the benefit of several IC processes in the same module. The goal was to develop a method to produce a stacked modular package on a small scale, and to verify the feasibility of the solution. The main focus has been to test the bare die connections to the interposer and the vertical connections between interposers. The structure enables also, e.g., thin discretes, and passive arrays to be assembled on the interposer, thus enabling system-in-package (SiP) solutions. The method has been tested using thin daisy chain dice and daisy chain vertical interconnections. The dimensions of the developed six chip modules were 14/spl times/8/spl times/0.8-1 mm. This module consists of three aramid-epoxy interposers, each containing two chips. The interposers were either 100 or 150-/spl mu/m thick, and the chips were thinned down to 90 /spl mu/s. Eutectic tin-lead solder bumps were used to mount the flip chips to the interposer. Solder-coated polymer spheres were used to stack the interposers on top of each other. The developed stacking process and vertical area interconnections by plastic core balls give good reliability and uniform stand-off height. Thermal cycling test +125/-40/spl deg/C until 2000 cycles proved reliability of the structure. Flip-chip failures were found after 500 cycles and only 1 of 32 vertical connection failures occurred during the test. Furthermore, this was caused, at least partly, by excess solder. Plastic ball as interconnection media between stacked layers gives good reliability and uniform stand-off height. |
| doi_str_mv | 10.1109/TADVP.2004.831860 |
| format | Article |
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The features of portable and handheld devices have increased whereas size is continually reduced. System-on-a-chip is the most effective size reduction approach, but is not a good business when excessively complex and oversized low yielding chips are required. A vertical package is a cost-effective solution to save placement and routing area on the board. Furthermore, a vertical module enables the benefit of several IC processes in the same module. The goal was to develop a method to produce a stacked modular package on a small scale, and to verify the feasibility of the solution. The main focus has been to test the bare die connections to the interposer and the vertical connections between interposers. The structure enables also, e.g., thin discretes, and passive arrays to be assembled on the interposer, thus enabling system-in-package (SiP) solutions. The method has been tested using thin daisy chain dice and daisy chain vertical interconnections. The dimensions of the developed six chip modules were 14/spl times/8/spl times/0.8-1 mm. This module consists of three aramid-epoxy interposers, each containing two chips. The interposers were either 100 or 150-/spl mu/m thick, and the chips were thinned down to 90 /spl mu/s. Eutectic tin-lead solder bumps were used to mount the flip chips to the interposer. Solder-coated polymer spheres were used to stack the interposers on top of each other. The developed stacking process and vertical area interconnections by plastic core balls give good reliability and uniform stand-off height. Thermal cycling test +125/-40/spl deg/C until 2000 cycles proved reliability of the structure. Flip-chip failures were found after 500 cycles and only 1 of 32 vertical connection failures occurred during the test. Furthermore, this was caused, at least partly, by excess solder. Plastic ball as interconnection media between stacked layers gives good reliability and uniform stand-off height.</description><identifier>ISSN: 1521-3323</identifier><identifier>EISSN: 1557-9980</identifier><identifier>DOI: 10.1109/TADVP.2004.831860</identifier><identifier>CODEN: ITAPFZ</identifier><language>eng</language><publisher>Piscataway, NY: IEEE</publisher><subject>Applied sciences ; Assembly systems ; Chips ; Design. Technologies. Operation analysis. Testing ; Electronics ; Electronics packaging ; Exact sciences and technology ; Failure ; Flip chip ; Handheld computers ; Integrated circuits ; Interconnections ; Joints ; Modular ; Modules ; Packages ; Plastics ; Polymers ; Routing ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Solders ; Stacking ; System-on-a-chip ; Testing ; Thermal cycling</subject><ispartof>IEEE transactions on advanced packaging, 2004-08, Vol.27 (3), p.461-466</ispartof><rights>2004 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2004</rights><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c414t-5e6d673b0f76f53142be21e4336fce8af99da743997f2a252baac54e86a107d3</citedby><cites>FETCH-LOGICAL-c414t-5e6d673b0f76f53142be21e4336fce8af99da743997f2a252baac54e86a107d3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1339445$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1339445$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=16188706$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Pienimaa, S.K.</creatorcontrib><creatorcontrib>Miettinen, J.</creatorcontrib><creatorcontrib>Ristolainen, E.</creatorcontrib><title>Stacked modular package</title><title>IEEE transactions on advanced packaging</title><addtitle>TADVP</addtitle><description>This paper reports on a vertical package developed to enable size reduction of electronics for miniaturized products. The features of portable and handheld devices have increased whereas size is continually reduced. System-on-a-chip is the most effective size reduction approach, but is not a good business when excessively complex and oversized low yielding chips are required. A vertical package is a cost-effective solution to save placement and routing area on the board. Furthermore, a vertical module enables the benefit of several IC processes in the same module. The goal was to develop a method to produce a stacked modular package on a small scale, and to verify the feasibility of the solution. The main focus has been to test the bare die connections to the interposer and the vertical connections between interposers. The structure enables also, e.g., thin discretes, and passive arrays to be assembled on the interposer, thus enabling system-in-package (SiP) solutions. The method has been tested using thin daisy chain dice and daisy chain vertical interconnections. The dimensions of the developed six chip modules were 14/spl times/8/spl times/0.8-1 mm. This module consists of three aramid-epoxy interposers, each containing two chips. The interposers were either 100 or 150-/spl mu/m thick, and the chips were thinned down to 90 /spl mu/s. Eutectic tin-lead solder bumps were used to mount the flip chips to the interposer. Solder-coated polymer spheres were used to stack the interposers on top of each other. The developed stacking process and vertical area interconnections by plastic core balls give good reliability and uniform stand-off height. Thermal cycling test +125/-40/spl deg/C until 2000 cycles proved reliability of the structure. Flip-chip failures were found after 500 cycles and only 1 of 32 vertical connection failures occurred during the test. Furthermore, this was caused, at least partly, by excess solder. Plastic ball as interconnection media between stacked layers gives good reliability and uniform stand-off height.</description><subject>Applied sciences</subject><subject>Assembly systems</subject><subject>Chips</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronics</subject><subject>Electronics packaging</subject><subject>Exact sciences and technology</subject><subject>Failure</subject><subject>Flip chip</subject><subject>Handheld computers</subject><subject>Integrated circuits</subject><subject>Interconnections</subject><subject>Joints</subject><subject>Modular</subject><subject>Modules</subject><subject>Packages</subject><subject>Plastics</subject><subject>Polymers</subject><subject>Routing</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Solders</subject><subject>Stacking</subject><subject>System-on-a-chip</subject><subject>Testing</subject><subject>Thermal cycling</subject><issn>1521-3323</issn><issn>1557-9980</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2004</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqFkE1LAzEQhoMoWKtnES9FUE9bJ9_JsdRPKChYvIY0m8jWbbcmuwf_vbtuoeBBZw4zwzzzwrwInWEYYwz6Zj65fXsZEwA2VhQrAXtogDmXmdYK9rue4IxSQg_RUUpLAMwUIwN0-lpb9-Hz0arKm9LG0aYd7bs_RgfBlsmfbOsQze_v5tPHbPb88DSdzDLHMKsz7kUuJF1AkCJwihlZeII9o1QE55UNWudWMqq1DMQSThbWOs68EhaDzOkQXfeym1h9Nj7VZlUk58vSrn3VJKO0ICCBs5a8-pMkWjBo439QCUIEyBa8-AUuqyau22-NUrRL2anhHnKxSin6YDaxWNn4ZTCYznnz47zpnDe98-3N5VbYJmfLEO3aFWl3KLBSEkTLnfdc4b3frSnVjHH6DVbciMM</recordid><startdate>20040801</startdate><enddate>20040801</enddate><creator>Pienimaa, S.K.</creator><creator>Miettinen, J.</creator><creator>Ristolainen, E.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>7TB</scope><scope>FR3</scope><scope>F28</scope></search><sort><creationdate>20040801</creationdate><title>Stacked modular package</title><author>Pienimaa, S.K. ; Miettinen, J. ; Ristolainen, E.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c414t-5e6d673b0f76f53142be21e4336fce8af99da743997f2a252baac54e86a107d3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Applied sciences</topic><topic>Assembly systems</topic><topic>Chips</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Electronics</topic><topic>Electronics packaging</topic><topic>Exact sciences and technology</topic><topic>Failure</topic><topic>Flip chip</topic><topic>Handheld computers</topic><topic>Integrated circuits</topic><topic>Interconnections</topic><topic>Joints</topic><topic>Modular</topic><topic>Modules</topic><topic>Packages</topic><topic>Plastics</topic><topic>Polymers</topic><topic>Routing</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Solders</topic><topic>Stacking</topic><topic>System-on-a-chip</topic><topic>Testing</topic><topic>Thermal cycling</topic><toplevel>online_resources</toplevel><creatorcontrib>Pienimaa, S.K.</creatorcontrib><creatorcontrib>Miettinen, J.</creatorcontrib><creatorcontrib>Ristolainen, E.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Mechanical & Transportation Engineering Abstracts</collection><collection>Engineering Research Database</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><jtitle>IEEE transactions on advanced packaging</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Pienimaa, S.K.</au><au>Miettinen, J.</au><au>Ristolainen, E.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Stacked modular package</atitle><jtitle>IEEE transactions on advanced packaging</jtitle><stitle>TADVP</stitle><date>2004-08-01</date><risdate>2004</risdate><volume>27</volume><issue>3</issue><spage>461</spage><epage>466</epage><pages>461-466</pages><issn>1521-3323</issn><eissn>1557-9980</eissn><coden>ITAPFZ</coden><abstract>This paper reports on a vertical package developed to enable size reduction of electronics for miniaturized products. The features of portable and handheld devices have increased whereas size is continually reduced. System-on-a-chip is the most effective size reduction approach, but is not a good business when excessively complex and oversized low yielding chips are required. A vertical package is a cost-effective solution to save placement and routing area on the board. Furthermore, a vertical module enables the benefit of several IC processes in the same module. The goal was to develop a method to produce a stacked modular package on a small scale, and to verify the feasibility of the solution. The main focus has been to test the bare die connections to the interposer and the vertical connections between interposers. The structure enables also, e.g., thin discretes, and passive arrays to be assembled on the interposer, thus enabling system-in-package (SiP) solutions. The method has been tested using thin daisy chain dice and daisy chain vertical interconnections. The dimensions of the developed six chip modules were 14/spl times/8/spl times/0.8-1 mm. This module consists of three aramid-epoxy interposers, each containing two chips. The interposers were either 100 or 150-/spl mu/m thick, and the chips were thinned down to 90 /spl mu/s. Eutectic tin-lead solder bumps were used to mount the flip chips to the interposer. Solder-coated polymer spheres were used to stack the interposers on top of each other. The developed stacking process and vertical area interconnections by plastic core balls give good reliability and uniform stand-off height. Thermal cycling test +125/-40/spl deg/C until 2000 cycles proved reliability of the structure. Flip-chip failures were found after 500 cycles and only 1 of 32 vertical connection failures occurred during the test. Furthermore, this was caused, at least partly, by excess solder. Plastic ball as interconnection media between stacked layers gives good reliability and uniform stand-off height.</abstract><cop>Piscataway, NY</cop><pub>IEEE</pub><doi>10.1109/TADVP.2004.831860</doi><tpages>6</tpages></addata></record> |
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| ispartof | IEEE transactions on advanced packaging, 2004-08, Vol.27 (3), p.461-466 |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Assembly systems Chips Design. Technologies. Operation analysis. Testing Electronics Electronics packaging Exact sciences and technology Failure Flip chip Handheld computers Integrated circuits Interconnections Joints Modular Modules Packages Plastics Polymers Routing Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Solders Stacking System-on-a-chip Testing Thermal cycling |
| title | Stacked modular package |
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