A single-chip CIF 30-Hz, H261, H263, and H263+ video encoder/decoder with embedded display controller
A single-chip video codec with embedded display controller for videotelephony applications is described. It encodes and decodes simultaneously up to 30 CIF pictures per second according to video-conferencing recommendations H261, H263 (all five options), and H263+ (six additional options). The die a...
Gespeichert in:
| Veröffentlicht in: | IEEE journal of solid-state circuits 1999-11, Vol.34 (11), p.1627-1633 |
|---|---|
| Hauptverfasser: | , , , , , , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 1633 |
|---|---|
| container_issue | 11 |
| container_start_page | 1627 |
| container_title | IEEE journal of solid-state circuits |
| container_volume | 34 |
| creator | Harrand, M. Sanches, J. Bellon, A. Bulone, J. Tournier, A. Deygas, O. Herluison, J.-C. Doise, D. Berrebi, E. |
| description | A single-chip video codec with embedded display controller for videotelephony applications is described. It encodes and decodes simultaneously up to 30 CIF pictures per second according to video-conferencing recommendations H261, H263 (all five options), and H263+ (six additional options). The die area is 132 mm/sup 2/ in a 0.35-/spl mu/m technology, and the power consumption is 1.4 W. The chip uses a distributed dedicated multiprocessor architecture; where computation-intensive functions are done by dedicated hardware, and where picture quality or standard dependent parts are done in software on dedicated programmable processors. Main architectural choices are discussed, and emphasis is put on hardware/software partitioning and codesign. |
| doi_str_mv | 10.1109/4.799872 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_28584182</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>799872</ieee_id><sourcerecordid>919936565</sourcerecordid><originalsourceid>FETCH-LOGICAL-c338t-8e2de65b9b251669a639d7db0642b8e55d0542925fe2593cfbeafa1c004539cd3</originalsourceid><addsrcrecordid>eNqF0U1Lw0AQBuBFFKxV8OxpTyrYtPud3WMp1hYKXhS8hc3uxK6kScy2Sv31to141Mu8M8zDXAahS0qGlBIzEsPUGJ2yI9SjUuqEpvzlGPUIoToxjJBTdBbj224UQtMegjGOoXotIXHL0ODJfIo5SWZfAzxjih4qH2Bb-UN3hz-ChxpD5WoP7cjDIfFnWC8xrHLwHjz2ITal3WJXV-u2Lktoz9FJYcsIFz_ZR8_T-6fJLFk8Pswn40XiONfrRAPzoGRuciapUsYqbnzqc6IEyzVI6YkUzDBZAJOGuyIHW1jqCBGSG-d5H910d5u2ft9AXGerEB2Upa2g3sTMUGO4kkru5PWfkmmpBdXsf5hSqY3eX7ztoGvrGFsosqYNK9tuM0qy_WsykXWv2dGrjgYA-GU_y2_s9oTC</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>27158985</pqid></control><display><type>article</type><title>A single-chip CIF 30-Hz, H261, H263, and H263+ video encoder/decoder with embedded display controller</title><source>IEEE Electronic Library (IEL)</source><creator>Harrand, M. ; Sanches, J. ; Bellon, A. ; Bulone, J. ; Tournier, A. ; Deygas, O. ; Herluison, J.-C. ; Doise, D. ; Berrebi, E.</creator><creatorcontrib>Harrand, M. ; Sanches, J. ; Bellon, A. ; Bulone, J. ; Tournier, A. ; Deygas, O. ; Herluison, J.-C. ; Doise, D. ; Berrebi, E.</creatorcontrib><description>A single-chip video codec with embedded display controller for videotelephony applications is described. It encodes and decodes simultaneously up to 30 CIF pictures per second according to video-conferencing recommendations H261, H263 (all five options), and H263+ (six additional options). The die area is 132 mm/sup 2/ in a 0.35-/spl mu/m technology, and the power consumption is 1.4 W. The chip uses a distributed dedicated multiprocessor architecture; where computation-intensive functions are done by dedicated hardware, and where picture quality or standard dependent parts are done in software on dedicated programmable processors. Main architectural choices are discussed, and emphasis is put on hardware/software partitioning and codesign.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/4.799872</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>IEEE</publisher><subject>Architecture ; Cameras ; Coders ; Computer programs ; Costs ; Decoding ; Displays ; Encoders ; Hardware ; Image coding ; ISDN ; Microprocessors ; Partitioning ; Pictures ; Software ; Software standards ; Video codecs</subject><ispartof>IEEE journal of solid-state circuits, 1999-11, Vol.34 (11), p.1627-1633</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c338t-8e2de65b9b251669a639d7db0642b8e55d0542925fe2593cfbeafa1c004539cd3</citedby><cites>FETCH-LOGICAL-c338t-8e2de65b9b251669a639d7db0642b8e55d0542925fe2593cfbeafa1c004539cd3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/799872$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/799872$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Harrand, M.</creatorcontrib><creatorcontrib>Sanches, J.</creatorcontrib><creatorcontrib>Bellon, A.</creatorcontrib><creatorcontrib>Bulone, J.</creatorcontrib><creatorcontrib>Tournier, A.</creatorcontrib><creatorcontrib>Deygas, O.</creatorcontrib><creatorcontrib>Herluison, J.-C.</creatorcontrib><creatorcontrib>Doise, D.</creatorcontrib><creatorcontrib>Berrebi, E.</creatorcontrib><title>A single-chip CIF 30-Hz, H261, H263, and H263+ video encoder/decoder with embedded display controller</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>A single-chip video codec with embedded display controller for videotelephony applications is described. It encodes and decodes simultaneously up to 30 CIF pictures per second according to video-conferencing recommendations H261, H263 (all five options), and H263+ (six additional options). The die area is 132 mm/sup 2/ in a 0.35-/spl mu/m technology, and the power consumption is 1.4 W. The chip uses a distributed dedicated multiprocessor architecture; where computation-intensive functions are done by dedicated hardware, and where picture quality or standard dependent parts are done in software on dedicated programmable processors. Main architectural choices are discussed, and emphasis is put on hardware/software partitioning and codesign.</description><subject>Architecture</subject><subject>Cameras</subject><subject>Coders</subject><subject>Computer programs</subject><subject>Costs</subject><subject>Decoding</subject><subject>Displays</subject><subject>Encoders</subject><subject>Hardware</subject><subject>Image coding</subject><subject>ISDN</subject><subject>Microprocessors</subject><subject>Partitioning</subject><subject>Pictures</subject><subject>Software</subject><subject>Software standards</subject><subject>Video codecs</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1999</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqF0U1Lw0AQBuBFFKxV8OxpTyrYtPud3WMp1hYKXhS8hc3uxK6kScy2Sv31to141Mu8M8zDXAahS0qGlBIzEsPUGJ2yI9SjUuqEpvzlGPUIoToxjJBTdBbj224UQtMegjGOoXotIXHL0ODJfIo5SWZfAzxjih4qH2Bb-UN3hz-ChxpD5WoP7cjDIfFnWC8xrHLwHjz2ITal3WJXV-u2Lktoz9FJYcsIFz_ZR8_T-6fJLFk8Pswn40XiONfrRAPzoGRuciapUsYqbnzqc6IEyzVI6YkUzDBZAJOGuyIHW1jqCBGSG-d5H910d5u2ft9AXGerEB2Upa2g3sTMUGO4kkru5PWfkmmpBdXsf5hSqY3eX7ztoGvrGFsosqYNK9tuM0qy_WsykXWv2dGrjgYA-GU_y2_s9oTC</recordid><startdate>19991101</startdate><enddate>19991101</enddate><creator>Harrand, M.</creator><creator>Sanches, J.</creator><creator>Bellon, A.</creator><creator>Bulone, J.</creator><creator>Tournier, A.</creator><creator>Deygas, O.</creator><creator>Herluison, J.-C.</creator><creator>Doise, D.</creator><creator>Berrebi, E.</creator><general>IEEE</general><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7U5</scope><scope>8FD</scope><scope>L7M</scope><scope>7SP</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>19991101</creationdate><title>A single-chip CIF 30-Hz, H261, H263, and H263+ video encoder/decoder with embedded display controller</title><author>Harrand, M. ; Sanches, J. ; Bellon, A. ; Bulone, J. ; Tournier, A. ; Deygas, O. ; Herluison, J.-C. ; Doise, D. ; Berrebi, E.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c338t-8e2de65b9b251669a639d7db0642b8e55d0542925fe2593cfbeafa1c004539cd3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1999</creationdate><topic>Architecture</topic><topic>Cameras</topic><topic>Coders</topic><topic>Computer programs</topic><topic>Costs</topic><topic>Decoding</topic><topic>Displays</topic><topic>Encoders</topic><topic>Hardware</topic><topic>Image coding</topic><topic>ISDN</topic><topic>Microprocessors</topic><topic>Partitioning</topic><topic>Pictures</topic><topic>Software</topic><topic>Software standards</topic><topic>Video codecs</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Harrand, M.</creatorcontrib><creatorcontrib>Sanches, J.</creatorcontrib><creatorcontrib>Bellon, A.</creatorcontrib><creatorcontrib>Bulone, J.</creatorcontrib><creatorcontrib>Tournier, A.</creatorcontrib><creatorcontrib>Deygas, O.</creatorcontrib><creatorcontrib>Herluison, J.-C.</creatorcontrib><creatorcontrib>Doise, D.</creatorcontrib><creatorcontrib>Berrebi, E.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Electronics & Communications Abstracts</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Harrand, M.</au><au>Sanches, J.</au><au>Bellon, A.</au><au>Bulone, J.</au><au>Tournier, A.</au><au>Deygas, O.</au><au>Herluison, J.-C.</au><au>Doise, D.</au><au>Berrebi, E.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A single-chip CIF 30-Hz, H261, H263, and H263+ video encoder/decoder with embedded display controller</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>1999-11-01</date><risdate>1999</risdate><volume>34</volume><issue>11</issue><spage>1627</spage><epage>1633</epage><pages>1627-1633</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>A single-chip video codec with embedded display controller for videotelephony applications is described. It encodes and decodes simultaneously up to 30 CIF pictures per second according to video-conferencing recommendations H261, H263 (all five options), and H263+ (six additional options). The die area is 132 mm/sup 2/ in a 0.35-/spl mu/m technology, and the power consumption is 1.4 W. The chip uses a distributed dedicated multiprocessor architecture; where computation-intensive functions are done by dedicated hardware, and where picture quality or standard dependent parts are done in software on dedicated programmable processors. Main architectural choices are discussed, and emphasis is put on hardware/software partitioning and codesign.</abstract><pub>IEEE</pub><doi>10.1109/4.799872</doi><tpages>7</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0018-9200 |
| ispartof | IEEE journal of solid-state circuits, 1999-11, Vol.34 (11), p.1627-1633 |
| issn | 0018-9200 1558-173X |
| language | eng |
| recordid | cdi_proquest_miscellaneous_28584182 |
| source | IEEE Electronic Library (IEL) |
| subjects | Architecture Cameras Coders Computer programs Costs Decoding Displays Encoders Hardware Image coding ISDN Microprocessors Partitioning Pictures Software Software standards Video codecs |
| title | A single-chip CIF 30-Hz, H261, H263, and H263+ video encoder/decoder with embedded display controller |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-31T02%3A03%3A47IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=A%20single-chip%20CIF%2030-Hz,%20H261,%20H263,%20and%20H263+%20video%20encoder/decoder%20with%20embedded%20display%20controller&rft.jtitle=IEEE%20journal%20of%20solid-state%20circuits&rft.au=Harrand,%20M.&rft.date=1999-11-01&rft.volume=34&rft.issue=11&rft.spage=1627&rft.epage=1633&rft.pages=1627-1633&rft.issn=0018-9200&rft.eissn=1558-173X&rft.coden=IJSCBC&rft_id=info:doi/10.1109/4.799872&rft_dat=%3Cproquest_RIE%3E919936565%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=27158985&rft_id=info:pmid/&rft_ieee_id=799872&rfr_iscdi=true |