Sample-set differential logic (SSDL) for complex high-speed VLSI

An improved CMOS logic circuitusing a differential cascode tree with sample and set phases of operation is presented. The sample-set differential logic (SSDL) circuit allows the use of several transistors in series in the cascode tree without significant speed degradation. Also, the signals arriving...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1986-04, Vol.21 (2), p.367-369
Hauptverfasser:	Grotjohn, T.A., Hoefflinger, B.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Circuit analysis computing Circuit properties CMOS logic circuits Digital circuits Digital systems Electric, optical and optoelectronic circuits Electronic circuits Electronics Error analysis Exact sciences and technology Integrated circuit noise Integrated circuit reliability Inverters Switching circuits Threshold voltage Very large scale integration
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