Routability checking for three-dimensional architectures

We present a novel symbolic routability checking approach for three-dimensional interconnect layout. The model considered is a general architecture that can fit into different applications, such as ASIC, multichip modules, field-programmable gate arrays, and reconfigurable computing architectures. T...

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Veröffentlicht in:	IEEE transactions on very large scale integration (VLSI) systems 2004-12, Vol.12 (12), p.1371-1374
Hauptverfasser:	Hung, W.N.N., Xiaoyu Song, Kam, T., Lerong Cheng, Guowu Yang
Format:	Artikel
Sprache:	eng
Schlagworte:	Application specific integrated circuits Applied sciences Architecture Benchmarks Boolean functions Computer-aided design (CAD) Data structures Design engineering Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Field programmable gate arrays Integrated circuit interconnections Integrated circuits Integrated circuits by function (including memories and processors) Joining processes layout Multichip modules routability Routing satisfiability Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Solvers Time measurements Very large scale integration Wire
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