Routability checking for three-dimensional architectures
We present a novel symbolic routability checking approach for three-dimensional interconnect layout. The model considered is a general architecture that can fit into different applications, such as ASIC, multichip modules, field-programmable gate arrays, and reconfigurable computing architectures. T...
Gespeichert in:
| Veröffentlicht in: | IEEE transactions on very large scale integration (VLSI) systems 2004-12, Vol.12 (12), p.1371-1374 |
|---|---|
| Hauptverfasser: | , , , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 1374 |
|---|---|
| container_issue | 12 |
| container_start_page | 1371 |
| container_title | IEEE transactions on very large scale integration (VLSI) systems |
| container_volume | 12 |
| creator | Hung, W.N.N. Xiaoyu Song Kam, T. Lerong Cheng Guowu Yang |
| description | We present a novel symbolic routability checking approach for three-dimensional interconnect layout. The model considered is a general architecture that can fit into different applications, such as ASIC, multichip modules, field-programmable gate arrays, and reconfigurable computing architectures. The method can incrementally incorporate additional constraints driven by timing, performance, and design. We used the latest satisfiability solver to validate the effectiveness of our approach. The experimental results demonstrate the encouraging performance on difficult routing benchmarks. |
| doi_str_mv | 10.1109/TVLSI.2004.837999 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_28550717</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>1407955</ieee_id><sourcerecordid>2583139071</sourcerecordid><originalsourceid>FETCH-LOGICAL-c386t-54386d1267488a49646382a67853df8997d1ce2b826c0caa06ce665cfffad7bc3</originalsourceid><addsrcrecordid>eNp9kEtLAzEUhQdRsFZ_gLgpguJm6s07WUrxUSgIWt2GNJOxqdOZmsws-u9NnYLgws09F-53DtyTZecIxgiBup2_z16nYwxAx5IIpdRBNkCMiTyt6jDtwEkuMYLj7CTGFQCiVMEgky9N15qFr3y7Hdmls5--_hiVTRi1y-BcXvi1q6NvalONTLBL3zrbdsHF0-yoNFV0Z3sdZm8P9_PJUz57fpxO7ma5JZK3OaNJCoS5oFIaqjjlRGLDhWSkKKVSokDW4YXE3II1Brh1nDNblqUpxMKSYXbd525C89W52Oq1j9ZVlald00WNJWMgkEjgzb8g4gJRkAhDQi__oKumC-nFqBUGKdKgCUI9ZEMTY3Cl3gS_NmGrEehd5_qnc73rXPedJ8_VPthEa6oymNr6-GvkhDCpcOIues47537PFIRijHwDfdGJZQ</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>920879204</pqid></control><display><type>article</type><title>Routability checking for three-dimensional architectures</title><source>IEEE Electronic Library (IEL)</source><creator>Hung, W.N.N. ; Xiaoyu Song ; Kam, T. ; Lerong Cheng ; Guowu Yang</creator><creatorcontrib>Hung, W.N.N. ; Xiaoyu Song ; Kam, T. ; Lerong Cheng ; Guowu Yang</creatorcontrib><description>We present a novel symbolic routability checking approach for three-dimensional interconnect layout. The model considered is a general architecture that can fit into different applications, such as ASIC, multichip modules, field-programmable gate arrays, and reconfigurable computing architectures. The method can incrementally incorporate additional constraints driven by timing, performance, and design. We used the latest satisfiability solver to validate the effectiveness of our approach. The experimental results demonstrate the encouraging performance on difficult routing benchmarks.</description><identifier>ISSN: 1063-8210</identifier><identifier>EISSN: 1557-9999</identifier><identifier>DOI: 10.1109/TVLSI.2004.837999</identifier><identifier>CODEN: IEVSE9</identifier><language>eng</language><publisher>Piscataway, NJ: IEEE</publisher><subject>Application specific integrated circuits ; Applied sciences ; Architecture ; Benchmarks ; Boolean functions ; Computer-aided design (CAD) ; Data structures ; Design engineering ; Design. Technologies. Operation analysis. Testing ; Electronics ; Exact sciences and technology ; Field programmable gate arrays ; Integrated circuit interconnections ; Integrated circuits ; Integrated circuits by function (including memories and processors) ; Joining processes ; layout ; Multichip modules ; routability ; Routing ; satisfiability ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Solvers ; Time measurements ; Very large scale integration ; Wire</subject><ispartof>IEEE transactions on very large scale integration (VLSI) systems, 2004-12, Vol.12 (12), p.1371-1374</ispartof><rights>2005 INIST-CNRS</rights><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2004</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c386t-54386d1267488a49646382a67853df8997d1ce2b826c0caa06ce665cfffad7bc3</citedby><cites>FETCH-LOGICAL-c386t-54386d1267488a49646382a67853df8997d1ce2b826c0caa06ce665cfffad7bc3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1407955$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,780,784,796,27924,27925,54758</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1407955$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=16335892$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Hung, W.N.N.</creatorcontrib><creatorcontrib>Xiaoyu Song</creatorcontrib><creatorcontrib>Kam, T.</creatorcontrib><creatorcontrib>Lerong Cheng</creatorcontrib><creatorcontrib>Guowu Yang</creatorcontrib><title>Routability checking for three-dimensional architectures</title><title>IEEE transactions on very large scale integration (VLSI) systems</title><addtitle>TVLSI</addtitle><description>We present a novel symbolic routability checking approach for three-dimensional interconnect layout. The model considered is a general architecture that can fit into different applications, such as ASIC, multichip modules, field-programmable gate arrays, and reconfigurable computing architectures. The method can incrementally incorporate additional constraints driven by timing, performance, and design. We used the latest satisfiability solver to validate the effectiveness of our approach. The experimental results demonstrate the encouraging performance on difficult routing benchmarks.</description><subject>Application specific integrated circuits</subject><subject>Applied sciences</subject><subject>Architecture</subject><subject>Benchmarks</subject><subject>Boolean functions</subject><subject>Computer-aided design (CAD)</subject><subject>Data structures</subject><subject>Design engineering</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Field programmable gate arrays</subject><subject>Integrated circuit interconnections</subject><subject>Integrated circuits</subject><subject>Integrated circuits by function (including memories and processors)</subject><subject>Joining processes</subject><subject>layout</subject><subject>Multichip modules</subject><subject>routability</subject><subject>Routing</subject><subject>satisfiability</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Solvers</subject><subject>Time measurements</subject><subject>Very large scale integration</subject><subject>Wire</subject><issn>1063-8210</issn><issn>1557-9999</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2004</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kEtLAzEUhQdRsFZ_gLgpguJm6s07WUrxUSgIWt2GNJOxqdOZmsws-u9NnYLgws09F-53DtyTZecIxgiBup2_z16nYwxAx5IIpdRBNkCMiTyt6jDtwEkuMYLj7CTGFQCiVMEgky9N15qFr3y7Hdmls5--_hiVTRi1y-BcXvi1q6NvalONTLBL3zrbdsHF0-yoNFV0Z3sdZm8P9_PJUz57fpxO7ma5JZK3OaNJCoS5oFIaqjjlRGLDhWSkKKVSokDW4YXE3II1Brh1nDNblqUpxMKSYXbd525C89W52Oq1j9ZVlald00WNJWMgkEjgzb8g4gJRkAhDQi__oKumC-nFqBUGKdKgCUI9ZEMTY3Cl3gS_NmGrEehd5_qnc73rXPedJ8_VPthEa6oymNr6-GvkhDCpcOIues47537PFIRijHwDfdGJZQ</recordid><startdate>20041201</startdate><enddate>20041201</enddate><creator>Hung, W.N.N.</creator><creator>Xiaoyu Song</creator><creator>Kam, T.</creator><creator>Lerong Cheng</creator><creator>Guowu Yang</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>RIA</scope><scope>RIE</scope><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20041201</creationdate><title>Routability checking for three-dimensional architectures</title><author>Hung, W.N.N. ; Xiaoyu Song ; Kam, T. ; Lerong Cheng ; Guowu Yang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c386t-54386d1267488a49646382a67853df8997d1ce2b826c0caa06ce665cfffad7bc3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2004</creationdate><topic>Application specific integrated circuits</topic><topic>Applied sciences</topic><topic>Architecture</topic><topic>Benchmarks</topic><topic>Boolean functions</topic><topic>Computer-aided design (CAD)</topic><topic>Data structures</topic><topic>Design engineering</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Field programmable gate arrays</topic><topic>Integrated circuit interconnections</topic><topic>Integrated circuits</topic><topic>Integrated circuits by function (including memories and processors)</topic><topic>Joining processes</topic><topic>layout</topic><topic>Multichip modules</topic><topic>routability</topic><topic>Routing</topic><topic>satisfiability</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Solvers</topic><topic>Time measurements</topic><topic>Very large scale integration</topic><topic>Wire</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Hung, W.N.N.</creatorcontrib><creatorcontrib>Xiaoyu Song</creatorcontrib><creatorcontrib>Kam, T.</creatorcontrib><creatorcontrib>Lerong Cheng</creatorcontrib><creatorcontrib>Guowu Yang</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Hung, W.N.N.</au><au>Xiaoyu Song</au><au>Kam, T.</au><au>Lerong Cheng</au><au>Guowu Yang</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Routability checking for three-dimensional architectures</atitle><jtitle>IEEE transactions on very large scale integration (VLSI) systems</jtitle><stitle>TVLSI</stitle><date>2004-12-01</date><risdate>2004</risdate><volume>12</volume><issue>12</issue><spage>1371</spage><epage>1374</epage><pages>1371-1374</pages><issn>1063-8210</issn><eissn>1557-9999</eissn><coden>IEVSE9</coden><abstract>We present a novel symbolic routability checking approach for three-dimensional interconnect layout. The model considered is a general architecture that can fit into different applications, such as ASIC, multichip modules, field-programmable gate arrays, and reconfigurable computing architectures. The method can incrementally incorporate additional constraints driven by timing, performance, and design. We used the latest satisfiability solver to validate the effectiveness of our approach. The experimental results demonstrate the encouraging performance on difficult routing benchmarks.</abstract><cop>Piscataway, NJ</cop><pub>IEEE</pub><doi>10.1109/TVLSI.2004.837999</doi><tpages>4</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 1063-8210 |
| ispartof | IEEE transactions on very large scale integration (VLSI) systems, 2004-12, Vol.12 (12), p.1371-1374 |
| issn | 1063-8210 1557-9999 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_28550717 |
| source | IEEE Electronic Library (IEL) |
| subjects | Application specific integrated circuits Applied sciences Architecture Benchmarks Boolean functions Computer-aided design (CAD) Data structures Design engineering Design. Technologies. Operation analysis. Testing Electronics Exact sciences and technology Field programmable gate arrays Integrated circuit interconnections Integrated circuits Integrated circuits by function (including memories and processors) Joining processes layout Multichip modules routability Routing satisfiability Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Solvers Time measurements Very large scale integration Wire |
| title | Routability checking for three-dimensional architectures |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-27T11%3A37%3A02IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Routability%20checking%20for%20three-dimensional%20architectures&rft.jtitle=IEEE%20transactions%20on%20very%20large%20scale%20integration%20(VLSI)%20systems&rft.au=Hung,%20W.N.N.&rft.date=2004-12-01&rft.volume=12&rft.issue=12&rft.spage=1371&rft.epage=1374&rft.pages=1371-1374&rft.issn=1063-8210&rft.eissn=1557-9999&rft.coden=IEVSE9&rft_id=info:doi/10.1109/TVLSI.2004.837999&rft_dat=%3Cproquest_RIE%3E2583139071%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=920879204&rft_id=info:pmid/&rft_ieee_id=1407955&rfr_iscdi=true |