Optimization of interconnection-induced breakdown voltage in junction isolated IC's using biased polysilicon field plates

Optimization of interconnection-induced breakdown voltage in junction isolated IC's using biased polysilicon field plates

The detrimental effect of high-voltage interconnection on the blocking capability of a junction isolated (JI) structure in a typical high-voltage integrated circuit (HVIC) process is investigated. A significant increase in breakdown voltage is realized using a novel biased polysilicon field plate te...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:IEEE transactions on electron devices 1997-01, Vol.44 (1), p.185-189
Hauptverfasser: Murray, A.F.J., Lane, W.A.
Format: Artikel
Sprache:eng
Schlagworte:
Breakdown voltage
Diodes
Electric breakdown
Integrated circuit interconnections
LAN interconnection
Microelectronics
Numerical simulation
Resistors
Wire
Wiring
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page 189
container_issue 1
container_start_page 185
container_title IEEE transactions on electron devices
container_volume 44
creator Murray, A.F.J.
Lane, W.A.
description The detrimental effect of high-voltage interconnection on the blocking capability of a junction isolated (JI) structure in a typical high-voltage integrated circuit (HVIC) process is investigated. A significant increase in breakdown voltage is realized using a novel biased polysilicon field plate technique. Fabricated devices show a large improvement in breakdown over the equivalent junction termination extension (JTE) case for the same wire width. Increases of 30% were observed for a three field plate scheme and 50% for four field plates. Breakdown voltages of up to 700 V were realized for a 50-/spl mu/m wide wire.
doi_str_mv 10.1109/16.554809
format Article
fullrecord <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_28528454</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>554809</ieee_id><sourcerecordid>28528454</sourcerecordid><originalsourceid>FETCH-LOGICAL-c209t-366b027bc77ded53d133359de6a7fc5908e01e04c27b68a1175766d23b8947903</originalsourceid><addsrcrecordid>eNo90D1PwzAQBmALgUQpDKxMnkAMKXYcf42o4qNSpS4wR45zqVxSO8QJqPx6XFoxne69Rze8CF1TMqOU6AcqZpwXiugTNKGcy0yLQpyiCSFUZZopdo4uYtykVRRFPkG7VTe4rfsxgwsehwY7P0Bvg_dg91HmfD1aqHHVg_mow7fHX6EdzBqSxJvR_ynsYmjNkNhifhfxGJ1f48qZmJIutLvoWpd-4sZBm5I9jZforDFthKvjnKL356e3-Wu2XL0s5o_LzOZEDxkToiK5rKyUNdSc1ZQxxnUNwsjGck0UEAqksMkIZSiVXApR56xSupCasCm6Pfzt-vA5QhzKrYsW2tZ4CGMsc8VzVfAiwfsDtH2IsYem7Hq3Nf2upKTcl1tSUR7KTfbmYB0A_Lvj8RfQYHZC</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>28528454</pqid></control><display><type>article</type><title>Optimization of interconnection-induced breakdown voltage in junction isolated IC's using biased polysilicon field plates</title><source>IEEE Electronic Library (IEL)</source><creator>Murray, A.F.J. ; Lane, W.A.</creator><creatorcontrib>Murray, A.F.J. ; Lane, W.A.</creatorcontrib><description>The detrimental effect of high-voltage interconnection on the blocking capability of a junction isolated (JI) structure in a typical high-voltage integrated circuit (HVIC) process is investigated. A significant increase in breakdown voltage is realized using a novel biased polysilicon field plate technique. Fabricated devices show a large improvement in breakdown over the equivalent junction termination extension (JTE) case for the same wire width. Increases of 30% were observed for a three field plate scheme and 50% for four field plates. Breakdown voltages of up to 700 V were realized for a 50-/spl mu/m wide wire.</description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/16.554809</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>IEEE</publisher><subject>Breakdown voltage ; Diodes ; Electric breakdown ; Integrated circuit interconnections ; LAN interconnection ; Microelectronics ; Numerical simulation ; Resistors ; Wire ; Wiring</subject><ispartof>IEEE transactions on electron devices, 1997-01, Vol.44 (1), p.185-189</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c209t-366b027bc77ded53d133359de6a7fc5908e01e04c27b68a1175766d23b8947903</citedby><cites>FETCH-LOGICAL-c209t-366b027bc77ded53d133359de6a7fc5908e01e04c27b68a1175766d23b8947903</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/554809$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/554809$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Murray, A.F.J.</creatorcontrib><creatorcontrib>Lane, W.A.</creatorcontrib><title>Optimization of interconnection-induced breakdown voltage in junction isolated IC's using biased polysilicon field plates</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>The detrimental effect of high-voltage interconnection on the blocking capability of a junction isolated (JI) structure in a typical high-voltage integrated circuit (HVIC) process is investigated. A significant increase in breakdown voltage is realized using a novel biased polysilicon field plate technique. Fabricated devices show a large improvement in breakdown over the equivalent junction termination extension (JTE) case for the same wire width. Increases of 30% were observed for a three field plate scheme and 50% for four field plates. Breakdown voltages of up to 700 V were realized for a 50-/spl mu/m wide wire.</description><subject>Breakdown voltage</subject><subject>Diodes</subject><subject>Electric breakdown</subject><subject>Integrated circuit interconnections</subject><subject>LAN interconnection</subject><subject>Microelectronics</subject><subject>Numerical simulation</subject><subject>Resistors</subject><subject>Wire</subject><subject>Wiring</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1997</creationdate><recordtype>article</recordtype><recordid>eNo90D1PwzAQBmALgUQpDKxMnkAMKXYcf42o4qNSpS4wR45zqVxSO8QJqPx6XFoxne69Rze8CF1TMqOU6AcqZpwXiugTNKGcy0yLQpyiCSFUZZopdo4uYtykVRRFPkG7VTe4rfsxgwsehwY7P0Bvg_dg91HmfD1aqHHVg_mow7fHX6EdzBqSxJvR_ynsYmjNkNhifhfxGJ1f48qZmJIutLvoWpd-4sZBm5I9jZforDFthKvjnKL356e3-Wu2XL0s5o_LzOZEDxkToiK5rKyUNdSc1ZQxxnUNwsjGck0UEAqksMkIZSiVXApR56xSupCasCm6Pfzt-vA5QhzKrYsW2tZ4CGMsc8VzVfAiwfsDtH2IsYem7Hq3Nf2upKTcl1tSUR7KTfbmYB0A_Lvj8RfQYHZC</recordid><startdate>199701</startdate><enddate>199701</enddate><creator>Murray, A.F.J.</creator><creator>Lane, W.A.</creator><general>IEEE</general><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>199701</creationdate><title>Optimization of interconnection-induced breakdown voltage in junction isolated IC's using biased polysilicon field plates</title><author>Murray, A.F.J. ; Lane, W.A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c209t-366b027bc77ded53d133359de6a7fc5908e01e04c27b68a1175766d23b8947903</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1997</creationdate><topic>Breakdown voltage</topic><topic>Diodes</topic><topic>Electric breakdown</topic><topic>Integrated circuit interconnections</topic><topic>LAN interconnection</topic><topic>Microelectronics</topic><topic>Numerical simulation</topic><topic>Resistors</topic><topic>Wire</topic><topic>Wiring</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Murray, A.F.J.</creatorcontrib><creatorcontrib>Lane, W.A.</creatorcontrib><collection>CrossRef</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Murray, A.F.J.</au><au>Lane, W.A.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Optimization of interconnection-induced breakdown voltage in junction isolated IC's using biased polysilicon field plates</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>1997-01</date><risdate>1997</risdate><volume>44</volume><issue>1</issue><spage>185</spage><epage>189</epage><pages>185-189</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>The detrimental effect of high-voltage interconnection on the blocking capability of a junction isolated (JI) structure in a typical high-voltage integrated circuit (HVIC) process is investigated. A significant increase in breakdown voltage is realized using a novel biased polysilicon field plate technique. Fabricated devices show a large improvement in breakdown over the equivalent junction termination extension (JTE) case for the same wire width. Increases of 30% were observed for a three field plate scheme and 50% for four field plates. Breakdown voltages of up to 700 V were realized for a 50-/spl mu/m wide wire.</abstract><pub>IEEE</pub><doi>10.1109/16.554809</doi><tpages>5</tpages></addata></record>
fulltext fulltext_linktorsrc
identifier ISSN: 0018-9383
ispartof IEEE transactions on electron devices, 1997-01, Vol.44 (1), p.185-189
issn 0018-9383
1557-9646
language eng
recordid cdi_proquest_miscellaneous_28528454
source IEEE Electronic Library (IEL)
subjects Breakdown voltage
Diodes
Electric breakdown
Integrated circuit interconnections
LAN interconnection
Microelectronics
Numerical simulation
Resistors
Wire
Wiring
title Optimization of interconnection-induced breakdown voltage in junction isolated IC's using biased polysilicon field plates
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-02T19%3A58%3A29IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Optimization%20of%20interconnection-induced%20breakdown%20voltage%20in%20junction%20isolated%20IC's%20using%20biased%20polysilicon%20field%20plates&rft.jtitle=IEEE%20transactions%20on%20electron%20devices&rft.au=Murray,%20A.F.J.&rft.date=1997-01&rft.volume=44&rft.issue=1&rft.spage=185&rft.epage=189&rft.pages=185-189&rft.issn=0018-9383&rft.eissn=1557-9646&rft.coden=IETDAI&rft_id=info:doi/10.1109/16.554809&rft_dat=%3Cproquest_RIE%3E28528454%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=28528454&rft_id=info:pmid/&rft_ieee_id=554809&rfr_iscdi=true