A partially insulated field-effect transistor (PiFET) as a candidate for scaled transistors
Highly manufacturable partially insulated field-effect transistors (PiFETs) were fabricated by using Si-SiGe epitaxial growth and selective SiGe etch process. Owing to these technologies, pseudo-silicon-on-insulator (SOI) structures, partially insulating oxide (PiOX) under source/drain (PUSD) and Pi...
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| Veröffentlicht in: | IEEE electron device letters 2004-06, Vol.25 (6), p.387-389 |
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| creator | Yeo, K.H. Oh, C.W. Kim, S.M. Kim, M.S. Lee, C.S. Lee, S.Y. Han, S.Y. Yoon, E.J. Cho, H.J. Lee, D.Y. Yoon, B.M. Rhee, H.S. Lee, B.C. Choe, J.D. Chung, I. Park, D. Kim, K. |
| description | Highly manufacturable partially insulated field-effect transistors (PiFETs) were fabricated by using Si-SiGe epitaxial growth and selective SiGe etch process. Owing to these technologies, pseudo-silicon-on-insulator (SOI) structures, partially insulating oxide (PiOX) under source/drain (PUSD) and PiOX under channel (PUC), could be easily realized with excellent structural and process advantages. We are demonstrating their preliminary characteristics and properties. Especially, in the PUSD PiFET, junction capacitance, leakage current, and DIBL in bulk devices could be reduced and the floating body problem in SOI devices was also cleared without any area penalty. Thus, this PiFET structure can be a promising candidate for the future DRAM cell transistor. |
| doi_str_mv | 10.1109/LED.2004.830064 |
| format | Article |
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Owing to these technologies, pseudo-silicon-on-insulator (SOI) structures, partially insulating oxide (PiOX) under source/drain (PUSD) and PiOX under channel (PUC), could be easily realized with excellent structural and process advantages. We are demonstrating their preliminary characteristics and properties. Especially, in the PUSD PiFET, junction capacitance, leakage current, and DIBL in bulk devices could be reduced and the floating body problem in SOI devices was also cleared without any area penalty. Thus, this PiFET structure can be a promising candidate for the future DRAM cell transistor.</description><subject>Capacitance</subject><subject>Devices</subject><subject>Drains</subject><subject>Epitaxial growth</subject><subject>Etching</subject><subject>FETs</subject><subject>Germanium silicon alloys</subject><subject>Insulation</subject><subject>Leakage current</subject><subject>Manufacturing processes</subject><subject>Oxides</subject><subject>Random access memory</subject><subject>Semiconductor devices</subject><subject>Silicon germanides</subject><subject>Silicon germanium</subject><subject>Transistors</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2004</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNqF0TtPwzAUBWALgUQpzAwsFgOPIe11_Ig9VqU8pEowwMRgOYktuUqTYidD_z2uilSJASYP_s714yB0SWBCCKjpcvEwyQHYRFIAwY7QiHAuM-CCHqMRFIxklIA4RWcxrgAIYwUboc8Z3pjQe9M0W-zbODSmtzV23jZ1Zp2zVY_7YNroY98FfPfmHxfv99hEbHBl2trXyWOXtmJlmpQ84HiOTpxpor34WcfoI4Xnz9ny9ellPltmFWOiz1QtnavAKcPS_akQylDnXAm8FKXLeSnBUmIs505YVRYlM8YVwHNecMqhpmN0u5-7Cd3XYGOv1z5WtmlMa7shaqlEDlwxluTNnzJXkD4K5P9QpuOppAle_4Krbghteq5WOaGcEgkJTfeoCl2MwTq9CX5twlYT0LvydCpP78rT-_JS4mqf8Nbag6aQ52nmN8cBlBY</recordid><startdate>20040601</startdate><enddate>20040601</enddate><creator>Yeo, K.H.</creator><creator>Oh, C.W.</creator><creator>Kim, S.M.</creator><creator>Kim, M.S.</creator><creator>Lee, C.S.</creator><creator>Lee, S.Y.</creator><creator>Han, S.Y.</creator><creator>Yoon, E.J.</creator><creator>Cho, H.J.</creator><creator>Lee, D.Y.</creator><creator>Yoon, B.M.</creator><creator>Rhee, H.S.</creator><creator>Lee, B.C.</creator><creator>Choe, J.D.</creator><creator>Chung, I.</creator><creator>Park, D.</creator><creator>Kim, K.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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Owing to these technologies, pseudo-silicon-on-insulator (SOI) structures, partially insulating oxide (PiOX) under source/drain (PUSD) and PiOX under channel (PUC), could be easily realized with excellent structural and process advantages. We are demonstrating their preliminary characteristics and properties. Especially, in the PUSD PiFET, junction capacitance, leakage current, and DIBL in bulk devices could be reduced and the floating body problem in SOI devices was also cleared without any area penalty. Thus, this PiFET structure can be a promising candidate for the future DRAM cell transistor.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/LED.2004.830064</doi><tpages>3</tpages></addata></record> |
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| subjects | Capacitance Devices Drains Epitaxial growth Etching FETs Germanium silicon alloys Insulation Leakage current Manufacturing processes Oxides Random access memory Semiconductor devices Silicon germanides Silicon germanium Transistors |
| title | A partially insulated field-effect transistor (PiFET) as a candidate for scaled transistors |
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