Interlevel dielectric failures in copper/low-k structures
Failure modes for inter-level dielectric layers under accelerated test conditions have been evaluated for a range of dielectric diffusion barriers in copper/low-k structures. The dominant failure mechanism for both constant voltage tests and ramped voltage tests was mechanical cracking at the dielec...
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| Veröffentlicht in: | IEEE transactions on device and materials reliability 2004-06, Vol.4 (2), p.148-152 |
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| container_title | IEEE transactions on device and materials reliability |
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| creator | Alers, G.B. Jow, K. Shaviv, R. Kooi, G. Ray, G.W. |
| description | Failure modes for inter-level dielectric layers under accelerated test conditions have been evaluated for a range of dielectric diffusion barriers in copper/low-k structures. The dominant failure mechanism for both constant voltage tests and ramped voltage tests was mechanical cracking at the dielectric barrier/low-k interface. Few occurrences of copper diffusion through the bulk ILD were observed. A simple model for the dominant failure mechanism is proposed which hypothesizes crack formation due to the electrostatic force between interdigitated lines followed by copper extrusion into the cracks. The proposed model is consistent with measurements of interfacial adhesion strengths in Cu/low-k stacks. |
| doi_str_mv | 10.1109/TDMR.2004.831989 |
| format | Magazinearticle |
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The dominant failure mechanism for both constant voltage tests and ramped voltage tests was mechanical cracking at the dielectric barrier/low-k interface. Few occurrences of copper diffusion through the bulk ILD were observed. A simple model for the dominant failure mechanism is proposed which hypothesizes crack formation due to the electrostatic force between interdigitated lines followed by copper extrusion into the cracks. The proposed model is consistent with measurements of interfacial adhesion strengths in Cu/low-k stacks.</description><identifier>ISSN: 1530-4388</identifier><identifier>EISSN: 1558-2574</identifier><identifier>DOI: 10.1109/TDMR.2004.831989</identifier><identifier>CODEN: ITDMA2</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Breakdown voltage ; Copper ; Cracks ; Devices ; Dielectric breakdown ; Dielectric materials ; Dielectrics ; Electric potential ; Extrapolation ; Failure ; Failure analysis ; Failure mechanisms ; Life estimation ; Life testing ; Silicon compounds ; Stress ; Voltage</subject><ispartof>IEEE transactions on device and materials reliability, 2004-06, Vol.4 (2), p.148-152</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. 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The dominant failure mechanism for both constant voltage tests and ramped voltage tests was mechanical cracking at the dielectric barrier/low-k interface. Few occurrences of copper diffusion through the bulk ILD were observed. A simple model for the dominant failure mechanism is proposed which hypothesizes crack formation due to the electrostatic force between interdigitated lines followed by copper extrusion into the cracks. The proposed model is consistent with measurements of interfacial adhesion strengths in Cu/low-k stacks.</description><subject>Breakdown voltage</subject><subject>Copper</subject><subject>Cracks</subject><subject>Devices</subject><subject>Dielectric breakdown</subject><subject>Dielectric materials</subject><subject>Dielectrics</subject><subject>Electric potential</subject><subject>Extrapolation</subject><subject>Failure</subject><subject>Failure analysis</subject><subject>Failure mechanisms</subject><subject>Life estimation</subject><subject>Life testing</subject><subject>Silicon compounds</subject><subject>Stress</subject><subject>Voltage</subject><issn>1530-4388</issn><issn>1558-2574</issn><fulltext>true</fulltext><rsrctype>magazinearticle</rsrctype><creationdate>2004</creationdate><recordtype>magazinearticle</recordtype><sourceid>RIE</sourceid><recordid>eNqNkU1LxDAQhoMouK7eBS_Fg566O0madnKU9RNWBFnPoU2n0LXb1qRV_Pe2VBA8iKcZmOd9YXgYO-Ww4Bz0cnP9-LwQANECJdeo99iMK4WhUEm0P-4SwkgiHrIj77cAXCcqnjH9UHfkKnqnKshLqsh2rrRBkZZV78gHZR3Ypm3JLavmI3wNfOd6242nY3ZQpJWnk-85Zy-3N5vVfbh-untYXa1DK1F0IWqtkryIEw5SQVxIVGgzJE1ZBnGWabAZIMcMolykMlc2zyzoNClsESW5knN2OfW2rnnryXdmV3pLVZXW1PTeaOCJhBj5QF78SQpEiZGK_wFGiEKPjee_wG3Tu3p412jBhUwwhgGCCbKu8d5RYVpX7lL3aTiY0Y0Z3ZjRjZncDJGzKVIS0Q8uOcYc5Red24mz</recordid><startdate>20040601</startdate><enddate>20040601</enddate><creator>Alers, G.B.</creator><creator>Jow, K.</creator><creator>Shaviv, R.</creator><creator>Kooi, G.</creator><creator>Ray, G.W.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. 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The dominant failure mechanism for both constant voltage tests and ramped voltage tests was mechanical cracking at the dielectric barrier/low-k interface. Few occurrences of copper diffusion through the bulk ILD were observed. A simple model for the dominant failure mechanism is proposed which hypothesizes crack formation due to the electrostatic force between interdigitated lines followed by copper extrusion into the cracks. The proposed model is consistent with measurements of interfacial adhesion strengths in Cu/low-k stacks.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/TDMR.2004.831989</doi><tpages>5</tpages></addata></record> |
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| source | IEEE Electronic Library (IEL) |
| subjects | Breakdown voltage Copper Cracks Devices Dielectric breakdown Dielectric materials Dielectrics Electric potential Extrapolation Failure Failure analysis Failure mechanisms Life estimation Life testing Silicon compounds Stress Voltage |
| title | Interlevel dielectric failures in copper/low-k structures |
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