Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability

Aggressive design using level-sensitive latches and wave pipelining has been proposed to meet the increasing need for higher performance digital systems. The optimal clocking problem for such designs has been formulated using an accurate timing model. However, this problem has been difficult to solv...

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Veröffentlicht in:IEEE transactions on computer-aided design of integrated circuits and systems 1995-12, Vol.14 (12), p.1526-1545
Hauptverfasser: Chuan-Hua Chang, Davidson, E.S., Sakallah, K.A.
Format: Artikel
Sprache:eng
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