Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability
Aggressive design using level-sensitive latches and wave pipelining has been proposed to meet the increasing need for higher performance digital systems. The optimal clocking problem for such designs has been formulated using an accurate timing model. However, this problem has been difficult to solv...
Gespeichert in:
Veröffentlicht in: | IEEE transactions on computer-aided design of integrated circuits and systems 1995-12, Vol.14 (12), p.1526-1545 |
---|---|
Hauptverfasser: | , , |
Format: | Artikel |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Schreiben Sie den ersten Kommentar!