Analysis of gate oxide thickness hot carrier effects in surface channel P-MOSFET's
The effect of hot carrier stress on surface channel p-MOS transistors is examined for two different oxide thicknesses. It is shown that the hot carrier failure time increases by 4 orders of magnitude when the oxide thickness is reduced from 10.7 nm to 7.2 nm for stress at low gate voltages (peak ele...
Gespeichert in:
| Veröffentlicht in: | IEEE transactions on electron devices 1995-01, Vol.42 (1), p.116-122 |
|---|---|
| Hauptverfasser: | , , |
| Format: | Artikel |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | 122 |
|---|---|
| container_issue | 1 |
| container_start_page | 116 |
| container_title | IEEE transactions on electron devices |
| container_volume | 42 |
| creator | Doyle, B.S. Mistry, K.R. Cheng-Liang Huang |
| description | The effect of hot carrier stress on surface channel p-MOS transistors is examined for two different oxide thicknesses. It is shown that the hot carrier failure time increases by 4 orders of magnitude when the oxide thickness is reduced from 10.7 nm to 7.2 nm for stress at low gate voltages (peak electron injection conditions), with no corresponding change in hot carrier resistance at high gate biases. Using a number of techniques, the various possible factors responsible for this are examined, and it is concluded that the increase in hot carrier resistance arises primarily due to a change in the position of hot electron injection peak, which moves further into the drain junction region for the thinner oxide transistors. Such effects as field-induced detrapping and the direct reduction in /spl Delta/V/sub t/ for thinner oxides are found to play secondary roles.< > |
| doi_str_mv | 10.1109/16.370027 |
| format | Article |
| fullrecord | <record><control><sourceid>proquest_RIE</sourceid><recordid>TN_cdi_proquest_miscellaneous_28432529</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>370027</ieee_id><sourcerecordid>28432529</sourcerecordid><originalsourceid>FETCH-LOGICAL-c337t-300b34629895cae1fd6847380b6e31ef6f04f5f6f779fc98d1c7e741886013b53</originalsourceid><addsrcrecordid>eNqNkDlPAzEQRi0EEuEoaKlcIBDFBl_ro4wiLgkUxFGvHGdMDMtu8Gwk-PcsWgQt1aeZefOKj5ADzsacM3fG9VgaxoTZICNelqZwWulNMmKM28JJK7fJDuJLP2qlxIjcTxpff2JC2kb67Dug7UdaAO2WKbw2gEiXbUeDzzlBphAjhA5paiiuc_QBaFj6poGa3hW3s4eL88cT3CNb0dcI-z-5S576_fSquJldXk8nN0WQ0nSFZGwulRbOujJ44HGhrTLSsrkGySHqyFQs-zDGxeDsggcDRnFrNeNyXspdcjx4V7l9XwN21VvCAHXtG2jXWIle7Jwz_wCVFKVwPXg6gCG3iBlitcrpzefPirPqu96K62qot2ePfqQeg69j9k1I-PsglbDCiB47HLAEAH_XwfEFPAV_pA</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>28432529</pqid></control><display><type>article</type><title>Analysis of gate oxide thickness hot carrier effects in surface channel P-MOSFET's</title><source>IEEE Electronic Library (IEL)</source><creator>Doyle, B.S. ; Mistry, K.R. ; Cheng-Liang Huang</creator><creatorcontrib>Doyle, B.S. ; Mistry, K.R. ; Cheng-Liang Huang</creatorcontrib><description>The effect of hot carrier stress on surface channel p-MOS transistors is examined for two different oxide thicknesses. It is shown that the hot carrier failure time increases by 4 orders of magnitude when the oxide thickness is reduced from 10.7 nm to 7.2 nm for stress at low gate voltages (peak electron injection conditions), with no corresponding change in hot carrier resistance at high gate biases. Using a number of techniques, the various possible factors responsible for this are examined, and it is concluded that the increase in hot carrier resistance arises primarily due to a change in the position of hot electron injection peak, which moves further into the drain junction region for the thinner oxide transistors. Such effects as field-induced detrapping and the direct reduction in /spl Delta/V/sub t/ for thinner oxides are found to play secondary roles.< ></description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/16.370027</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Charge carriers ; Degradation ; Electron traps ; Electronics ; Exact sciences and technology ; Hot carrier effects ; Hot carriers ; Impact ionization ; Low voltage ; MOSFET circuits ; Secondary generated hot electron injection ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Stress ; Transistors</subject><ispartof>IEEE transactions on electron devices, 1995-01, Vol.42 (1), p.116-122</ispartof><rights>1995 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c337t-300b34629895cae1fd6847380b6e31ef6f04f5f6f779fc98d1c7e741886013b53</citedby><cites>FETCH-LOGICAL-c337t-300b34629895cae1fd6847380b6e31ef6f04f5f6f779fc98d1c7e741886013b53</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/370027$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>315,781,785,797,4025,27925,27926,27927,54760</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/370027$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=3428272$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Doyle, B.S.</creatorcontrib><creatorcontrib>Mistry, K.R.</creatorcontrib><creatorcontrib>Cheng-Liang Huang</creatorcontrib><title>Analysis of gate oxide thickness hot carrier effects in surface channel P-MOSFET's</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>The effect of hot carrier stress on surface channel p-MOS transistors is examined for two different oxide thicknesses. It is shown that the hot carrier failure time increases by 4 orders of magnitude when the oxide thickness is reduced from 10.7 nm to 7.2 nm for stress at low gate voltages (peak electron injection conditions), with no corresponding change in hot carrier resistance at high gate biases. Using a number of techniques, the various possible factors responsible for this are examined, and it is concluded that the increase in hot carrier resistance arises primarily due to a change in the position of hot electron injection peak, which moves further into the drain junction region for the thinner oxide transistors. Such effects as field-induced detrapping and the direct reduction in /spl Delta/V/sub t/ for thinner oxides are found to play secondary roles.< ></description><subject>Applied sciences</subject><subject>Charge carriers</subject><subject>Degradation</subject><subject>Electron traps</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Hot carrier effects</subject><subject>Hot carriers</subject><subject>Impact ionization</subject><subject>Low voltage</subject><subject>MOSFET circuits</subject><subject>Secondary generated hot electron injection</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Stress</subject><subject>Transistors</subject><issn>0018-9383</issn><issn>1557-9646</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1995</creationdate><recordtype>article</recordtype><recordid>eNqNkDlPAzEQRi0EEuEoaKlcIBDFBl_ro4wiLgkUxFGvHGdMDMtu8Gwk-PcsWgQt1aeZefOKj5ADzsacM3fG9VgaxoTZICNelqZwWulNMmKM28JJK7fJDuJLP2qlxIjcTxpff2JC2kb67Dug7UdaAO2WKbw2gEiXbUeDzzlBphAjhA5paiiuc_QBaFj6poGa3hW3s4eL88cT3CNb0dcI-z-5S576_fSquJldXk8nN0WQ0nSFZGwulRbOujJ44HGhrTLSsrkGySHqyFQs-zDGxeDsggcDRnFrNeNyXspdcjx4V7l9XwN21VvCAHXtG2jXWIle7Jwz_wCVFKVwPXg6gCG3iBlitcrpzefPirPqu96K62qot2ePfqQeg69j9k1I-PsglbDCiB47HLAEAH_XwfEFPAV_pA</recordid><startdate>199501</startdate><enddate>199501</enddate><creator>Doyle, B.S.</creator><creator>Mistry, K.R.</creator><creator>Cheng-Liang Huang</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>7U5</scope></search><sort><creationdate>199501</creationdate><title>Analysis of gate oxide thickness hot carrier effects in surface channel P-MOSFET's</title><author>Doyle, B.S. ; Mistry, K.R. ; Cheng-Liang Huang</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c337t-300b34629895cae1fd6847380b6e31ef6f04f5f6f779fc98d1c7e741886013b53</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1995</creationdate><topic>Applied sciences</topic><topic>Charge carriers</topic><topic>Degradation</topic><topic>Electron traps</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Hot carrier effects</topic><topic>Hot carriers</topic><topic>Impact ionization</topic><topic>Low voltage</topic><topic>MOSFET circuits</topic><topic>Secondary generated hot electron injection</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Stress</topic><topic>Transistors</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Doyle, B.S.</creatorcontrib><creatorcontrib>Mistry, K.R.</creatorcontrib><creatorcontrib>Cheng-Liang Huang</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Solid State and Superconductivity Abstracts</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Doyle, B.S.</au><au>Mistry, K.R.</au><au>Cheng-Liang Huang</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Analysis of gate oxide thickness hot carrier effects in surface channel P-MOSFET's</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>1995-01</date><risdate>1995</risdate><volume>42</volume><issue>1</issue><spage>116</spage><epage>122</epage><pages>116-122</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>The effect of hot carrier stress on surface channel p-MOS transistors is examined for two different oxide thicknesses. It is shown that the hot carrier failure time increases by 4 orders of magnitude when the oxide thickness is reduced from 10.7 nm to 7.2 nm for stress at low gate voltages (peak electron injection conditions), with no corresponding change in hot carrier resistance at high gate biases. Using a number of techniques, the various possible factors responsible for this are examined, and it is concluded that the increase in hot carrier resistance arises primarily due to a change in the position of hot electron injection peak, which moves further into the drain junction region for the thinner oxide transistors. Such effects as field-induced detrapping and the direct reduction in /spl Delta/V/sub t/ for thinner oxides are found to play secondary roles.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/16.370027</doi><tpages>7</tpages></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | ISSN: 0018-9383 |
| ispartof | IEEE transactions on electron devices, 1995-01, Vol.42 (1), p.116-122 |
| issn | 0018-9383 1557-9646 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_28432529 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Charge carriers Degradation Electron traps Electronics Exact sciences and technology Hot carrier effects Hot carriers Impact ionization Low voltage MOSFET circuits Secondary generated hot electron injection Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Stress Transistors |
| title | Analysis of gate oxide thickness hot carrier effects in surface channel P-MOSFET's |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-18T10%3A30%3A44IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_RIE&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Analysis%20of%20gate%20oxide%20thickness%20hot%20carrier%20effects%20in%20surface%20channel%20P-MOSFET's&rft.jtitle=IEEE%20transactions%20on%20electron%20devices&rft.au=Doyle,%20B.S.&rft.date=1995-01&rft.volume=42&rft.issue=1&rft.spage=116&rft.epage=122&rft.pages=116-122&rft.issn=0018-9383&rft.eissn=1557-9646&rft.coden=IETDAI&rft_id=info:doi/10.1109/16.370027&rft_dat=%3Cproquest_RIE%3E28432529%3C/proquest_RIE%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=28432529&rft_id=info:pmid/&rft_ieee_id=370027&rfr_iscdi=true |