An 80-MFLOPS (peak) 64-b microprocessor for parallel computer

An 80-MFLOPS (peak) 64-b microprocessor for parallel computer

An 80-MFLOPS (peak) 64-b microprocessor that employs superscalar architecture to execute two instructions simultaneously in one 25-ns cycle, including the combination of 64-b floating-point add and multiply instructions, is described. The processor implemented in a 0.8- mu m CMOS technology contains...

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Veröffentlicht in:IEEE journal of solid-state circuits 1992-03, Vol.27 (3), p.365-372
Hauptverfasser: Nakano, H., Nakajima, M., Nakakura, Y., Yoshida, T., Goi, Y., Nakai, Y., Segawa, R., Kishida, T., Kadota, H.
Format: Artikel
Sprache:eng
Schlagworte:
Applied sciences
CMOS process
CMOS technology
Computer aided instruction
Computer architecture
Concurrent computing
Electronics
Exact sciences and technology
Integrated circuits
Integrated circuits by function (including memories and processors)
Microprocessors
Pipelines
Reduced instruction set computing
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Very large scale integration
VLIW
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Zusammenfassung:An 80-MFLOPS (peak) 64-b microprocessor that employs superscalar architecture to execute two instructions simultaneously in one 25-ns cycle, including the combination of 64-b floating-point add and multiply instructions, is described. The processor implemented in a 0.8- mu m CMOS technology contains 1300 K transistors. The processor also employs a RISC architecture and Harvard-style bus organization. The authors provide an overview of the processor, especially focusing on processor architecture, floating-point hardware, and performance.< >
ISSN:0018-9200
1558-173X
DOI:10.1109/4.121559