Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits
This paper describes substrate noise reduction techniques for synchronous CMOS circuits. Low-noise digital design techniques have been implemented and measured on a mixed-signal chip, fabricated in a 0.35 /spl mu/m CMOS process on an EPI-type substrate with 10 /spl Omega/cm EPI resistivity and 4 /sp...
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| Veröffentlicht in: | IEEE journal of solid-state circuits 2002-11, Vol.37 (11), p.1383-1395 |
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| container_title | IEEE journal of solid-state circuits |
| container_volume | 37 |
| creator | Badaroglu, M. van Heijningen, M. Gravot, V. Compiet, J. Donnay, S. Gielen, G.G.E. De Man, H.J. |
| description | This paper describes substrate noise reduction techniques for synchronous CMOS circuits. Low-noise digital design techniques have been implemented and measured on a mixed-signal chip, fabricated in a 0.35 /spl mu/m CMOS process on an EPI-type substrate with 10 /spl Omega/cm EPI resistivity and 4 /spl mu/m EPI layer thickness. The test chip contains one reference design and two digital low-noise designs with the same basic architecture. Measurements show more than a factor of 2 on average in r.m.s. noise reduction with penalties of 3% in area and 4% in power for the low-noise design employing a supply-current waveform-shaping technique based on a clock tree with latencies. The second low-noise design employing separate substrate bias for both n- and p-wells, dual-supply, and on-chip decoupling achieves more than a factor of 2 reduction in r.m.s. noise, with, however, a 70% increase in area, but with a 5% decrease in power consumption. |
| doi_str_mv | 10.1109/JSSC.2002.803938 |
| format | Article |
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Low-noise digital design techniques have been implemented and measured on a mixed-signal chip, fabricated in a 0.35 /spl mu/m CMOS process on an EPI-type substrate with 10 /spl Omega/cm EPI resistivity and 4 /spl mu/m EPI layer thickness. The test chip contains one reference design and two digital low-noise designs with the same basic architecture. Measurements show more than a factor of 2 on average in r.m.s. noise reduction with penalties of 3% in area and 4% in power for the low-noise design employing a supply-current waveform-shaping technique based on a clock tree with latencies. The second low-noise design employing separate substrate bias for both n- and p-wells, dual-supply, and on-chip decoupling achieves more than a factor of 2 reduction in r.m.s. noise, with, however, a 70% increase in area, but with a 5% decrease in power consumption.</description><identifier>ISSN: 0018-9200</identifier><identifier>EISSN: 1558-173X</identifier><identifier>DOI: 10.1109/JSSC.2002.803938</identifier><identifier>CODEN: IJSCBC</identifier><language>eng</language><publisher>New York: IEEE</publisher><subject>Area measurement ; Chips (electronics) ; Circuit testing ; Circuits ; CMOS ; CMOS digital integrated circuits ; CMOS process ; CMOS technology ; Conductivity ; Decoupling ; Design factors ; Digital circuits ; Noise reduction ; Semiconductor device measurement ; Synchronous ; Thickness measurement</subject><ispartof>IEEE journal of solid-state circuits, 2002-11, Vol.37 (11), p.1383-1395</ispartof><rights>Copyright The Institute of Electrical and Electronics Engineers, Inc. (IEEE) 2002</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c351t-c560ace3d9492247644bc610dcfe9450878d433b1ccdf86658801c8faeb3652e3</citedby><cites>FETCH-LOGICAL-c351t-c560ace3d9492247644bc610dcfe9450878d433b1ccdf86658801c8faeb3652e3</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/1046080$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/1046080$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc></links><search><creatorcontrib>Badaroglu, M.</creatorcontrib><creatorcontrib>van Heijningen, M.</creatorcontrib><creatorcontrib>Gravot, V.</creatorcontrib><creatorcontrib>Compiet, J.</creatorcontrib><creatorcontrib>Donnay, S.</creatorcontrib><creatorcontrib>Gielen, G.G.E.</creatorcontrib><creatorcontrib>De Man, H.J.</creatorcontrib><title>Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits</title><title>IEEE journal of solid-state circuits</title><addtitle>JSSC</addtitle><description>This paper describes substrate noise reduction techniques for synchronous CMOS circuits. Low-noise digital design techniques have been implemented and measured on a mixed-signal chip, fabricated in a 0.35 /spl mu/m CMOS process on an EPI-type substrate with 10 /spl Omega/cm EPI resistivity and 4 /spl mu/m EPI layer thickness. The test chip contains one reference design and two digital low-noise designs with the same basic architecture. Measurements show more than a factor of 2 on average in r.m.s. noise reduction with penalties of 3% in area and 4% in power for the low-noise design employing a supply-current waveform-shaping technique based on a clock tree with latencies. The second low-noise design employing separate substrate bias for both n- and p-wells, dual-supply, and on-chip decoupling achieves more than a factor of 2 reduction in r.m.s. noise, with, however, a 70% increase in area, but with a 5% decrease in power consumption.</description><subject>Area measurement</subject><subject>Chips (electronics)</subject><subject>Circuit testing</subject><subject>Circuits</subject><subject>CMOS</subject><subject>CMOS digital integrated circuits</subject><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Conductivity</subject><subject>Decoupling</subject><subject>Design factors</subject><subject>Digital circuits</subject><subject>Noise reduction</subject><subject>Semiconductor device measurement</subject><subject>Synchronous</subject><subject>Thickness measurement</subject><issn>0018-9200</issn><issn>1558-173X</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>2002</creationdate><recordtype>article</recordtype><sourceid>RIE</sourceid><recordid>eNp9kb9vEzEcxS1EJULLjsRiMcB0wT_v7BGdKC1q1SEgsZ0c-3uJq4sdbB9tVv5ynIYBMTDZ1vu8p-_XD6HXlCwpJfrDl9WqXzJC2FIRrrl6hhZUStXQjn9_jhaEUNXoqr9AL3O-r08hFF2gX7dQttHFKW4O2ASH4XEPye8gFDPhn_U6emuKjwGPMeE8r3NJpgAO0WfACdxsn1QfcH97t8I7_wiuyX4Tqv-6z_jBly3Oh2C3KYY4Z-z8xh_DrU929iVfoLPRTBle_TnP0bfLT1_7q-bm7vN1__GmsVzS0ljZEmOBOy00Y6JrhVjblhJnR9BCEtUpJzhfU2vdqNpWKkWoVaOBNW8lA36O3p9y9yn-mCGXYeezhWkyAepcgyadli0TopLv_ksyxZVupazg23_A-zinunlN00x1kildIXKCbIo5JxiHff1gkw4DJcOxu-HY3XDsbjh1Vy1vThYPAH_hoiWV-A1TAJdi</recordid><startdate>20021101</startdate><enddate>20021101</enddate><creator>Badaroglu, M.</creator><creator>van Heijningen, M.</creator><creator>Gravot, V.</creator><creator>Compiet, J.</creator><creator>Donnay, S.</creator><creator>Gielen, G.G.E.</creator><creator>De Man, H.J.</creator><general>IEEE</general><general>The Institute of Electrical and Electronics Engineers, Inc. (IEEE)</general><scope>RIA</scope><scope>RIE</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope><scope>F28</scope><scope>FR3</scope></search><sort><creationdate>20021101</creationdate><title>Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits</title><author>Badaroglu, M. ; van Heijningen, M. ; Gravot, V. ; Compiet, J. ; Donnay, S. ; Gielen, G.G.E. ; De Man, H.J.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c351t-c560ace3d9492247644bc610dcfe9450878d433b1ccdf86658801c8faeb3652e3</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>2002</creationdate><topic>Area measurement</topic><topic>Chips (electronics)</topic><topic>Circuit testing</topic><topic>Circuits</topic><topic>CMOS</topic><topic>CMOS digital integrated circuits</topic><topic>CMOS process</topic><topic>CMOS technology</topic><topic>Conductivity</topic><topic>Decoupling</topic><topic>Design factors</topic><topic>Digital circuits</topic><topic>Noise reduction</topic><topic>Semiconductor device measurement</topic><topic>Synchronous</topic><topic>Thickness measurement</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Badaroglu, M.</creatorcontrib><creatorcontrib>van Heijningen, M.</creatorcontrib><creatorcontrib>Gravot, V.</creatorcontrib><creatorcontrib>Compiet, J.</creatorcontrib><creatorcontrib>Donnay, S.</creatorcontrib><creatorcontrib>Gielen, G.G.E.</creatorcontrib><creatorcontrib>De Man, H.J.</creatorcontrib><collection>IEEE All-Society Periodicals Package (ASPP) 1998-Present</collection><collection>IEEE Electronic Library (IEL)</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>ANTE: Abstracts in New Technology & Engineering</collection><collection>Engineering Research Database</collection><jtitle>IEEE journal of solid-state circuits</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Badaroglu, M.</au><au>van Heijningen, M.</au><au>Gravot, V.</au><au>Compiet, J.</au><au>Donnay, S.</au><au>Gielen, G.G.E.</au><au>De Man, H.J.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits</atitle><jtitle>IEEE journal of solid-state circuits</jtitle><stitle>JSSC</stitle><date>2002-11-01</date><risdate>2002</risdate><volume>37</volume><issue>11</issue><spage>1383</spage><epage>1395</epage><pages>1383-1395</pages><issn>0018-9200</issn><eissn>1558-173X</eissn><coden>IJSCBC</coden><abstract>This paper describes substrate noise reduction techniques for synchronous CMOS circuits. Low-noise digital design techniques have been implemented and measured on a mixed-signal chip, fabricated in a 0.35 /spl mu/m CMOS process on an EPI-type substrate with 10 /spl Omega/cm EPI resistivity and 4 /spl mu/m EPI layer thickness. The test chip contains one reference design and two digital low-noise designs with the same basic architecture. Measurements show more than a factor of 2 on average in r.m.s. noise reduction with penalties of 3% in area and 4% in power for the low-noise design employing a supply-current waveform-shaping technique based on a clock tree with latencies. The second low-noise design employing separate substrate bias for both n- and p-wells, dual-supply, and on-chip decoupling achieves more than a factor of 2 reduction in r.m.s. noise, with, however, a 70% increase in area, but with a 5% decrease in power consumption.</abstract><cop>New York</cop><pub>IEEE</pub><doi>10.1109/JSSC.2002.803938</doi><tpages>13</tpages></addata></record> |
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| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Area measurement Chips (electronics) Circuit testing Circuits CMOS CMOS digital integrated circuits CMOS process CMOS technology Conductivity Decoupling Design factors Digital circuits Noise reduction Semiconductor device measurement Synchronous Thickness measurement |
| title | Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits |
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