Scalable ATM network interface design using parallel RISC processors architecture

In this work, a high-speed scalable ATM network interface has been designed and simulated. The interface has two processing engines, one for the transmission and the other for receiving side. Two specialized single-issue RISC cores supported with three stages pipeline and forwarding engine, have been used to process the network interface functions and ATM protocols. In addition, the interface architecture has Content Addressable Memory, five First-In-First-Out buffers, two simple Direct Memory Access units, two dual-port RAM, host interface, and transmission lines interface. The performance evaluation of the network interface has been measured through the development of a VHDL-based cycle accurate simulator. The results have shown that such network interface is scalable and could support a wire-speed of 2.4 Gb/s when the RISC cores run at a clock rate of about 170 MHz.