Memory system reliability improvement through associative cache redundancy

The development of a VLSI device that provides memory system self-testing and redundancy without incurring the overhead penalties of error-correction coding or page-swapping techniques is described. This device isolates hard errors in system memory by writing a true and complement pattern to each sy...

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Bibliographische Detailangaben

Veröffentlicht in:	IEEE journal of solid-state circuits 1991-03, Vol.26 (3), p.404-409
Hauptverfasser:	Lucente, M.A., Harris, C.H., Muir, R.M.
Format:	Artikel
Sprache:	eng
Schlagworte:	Built-in self-test Cache memory Circuit faults Error correction Redundancy Reliability System testing System-on-a-chip Very large scale integration Writing
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