A low-capacitance bipolar/BiCMOS isolation technology. I. Concept, fabrication process, and characterization

A device isolation structure for low-parasitic bipolar transistor integration is presented. The concept involves two selective epitaxial growth steps (SEG) and two polishing cycles which replace the collector-epitaxy and the deep/shallow trench formation in conventional device isolation. With an opt...

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Veröffentlicht in:	IEEE transactions on electron devices 1994-08, Vol.41 (8), p.1379-1387
Hauptverfasser:	Burghartz, J.N., McIntosh, R.C., Stanis, C.L.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences BiCMOS integrated circuits Bipolar transistors Capacitance Carbon capture and storage CMOS technology Design. Technologies. Operation analysis. Testing Electronics Epitaxial growth Exact sciences and technology Fabrication Integrated circuit interconnections Integrated circuits Isolation technology Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Substrates
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