A low-capacitance bipolar/BiCMOS isolation technology. I. Concept, fabrication process, and characterization
A device isolation structure for low-parasitic bipolar transistor integration is presented. The concept involves two selective epitaxial growth steps (SEG) and two polishing cycles which replace the collector-epitaxy and the deep/shallow trench formation in conventional device isolation. With an opt...
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| Veröffentlicht in: | IEEE transactions on electron devices 1994-08, Vol.41 (8), p.1379-1387 |
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| container_end_page | 1387 |
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| container_title | IEEE transactions on electron devices |
| container_volume | 41 |
| creator | Burghartz, J.N. McIntosh, R.C. Stanis, C.L. |
| description | A device isolation structure for low-parasitic bipolar transistor integration is presented. The concept involves two selective epitaxial growth steps (SEG) and two polishing cycles which replace the collector-epitaxy and the deep/shallow trench formation in conventional device isolation. With an optimum device layout, the collector-substrate capacitance is reduced to /spl sime/30%, the collector-base capacitance to /spl sime/70%, and the extrinsic base contact resistance to |
| doi_str_mv | 10.1109/16.297733 |
| format | Article |
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The combination of SEG and polishing makes it possible to form SOI regions with locally different SOI thicknesses on the same wafer, so that fully depleted CMOS and vertical bipolar transistors can be combined in a SOI-BiCMOS technology.< ></description><identifier>ISSN: 0018-9383</identifier><identifier>EISSN: 1557-9646</identifier><identifier>DOI: 10.1109/16.297733</identifier><identifier>CODEN: IETDAI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; BiCMOS integrated circuits ; Bipolar transistors ; Capacitance ; Carbon capture and storage ; CMOS technology ; Design. Technologies. Operation analysis. Testing ; Electronics ; Epitaxial growth ; Exact sciences and technology ; Fabrication ; Integrated circuit interconnections ; Integrated circuits ; Isolation technology ; Semiconductor electronics. Microelectronics. Optoelectronics. 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I. Concept, fabrication process, and characterization</title><title>IEEE transactions on electron devices</title><addtitle>TED</addtitle><description>A device isolation structure for low-parasitic bipolar transistor integration is presented. The concept involves two selective epitaxial growth steps (SEG) and two polishing cycles which replace the collector-epitaxy and the deep/shallow trench formation in conventional device isolation. With an optimum device layout, the collector-substrate capacitance is reduced to /spl sime/30%, the collector-base capacitance to /spl sime/70%, and the extrinsic base contact resistance to <50% compared to trench isolation. The combination of SEG and polishing makes it possible to form SOI regions with locally different SOI thicknesses on the same wafer, so that fully depleted CMOS and vertical bipolar transistors can be combined in a SOI-BiCMOS technology.< ></description><subject>Applied sciences</subject><subject>BiCMOS integrated circuits</subject><subject>Bipolar transistors</subject><subject>Capacitance</subject><subject>Carbon capture and storage</subject><subject>CMOS technology</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronics</subject><subject>Epitaxial growth</subject><subject>Exact sciences and technology</subject><subject>Fabrication</subject><subject>Integrated circuit interconnections</subject><subject>Integrated circuits</subject><subject>Isolation technology</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Solid state devices</topic><topic>Substrates</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Burghartz, J.N.</creatorcontrib><creatorcontrib>McIntosh, R.C.</creatorcontrib><creatorcontrib>Stanis, C.L.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Solid State and Superconductivity Abstracts</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Burghartz, J.N.</au><au>McIntosh, R.C.</au><au>Stanis, C.L.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A low-capacitance bipolar/BiCMOS isolation technology. I. Concept, fabrication process, and characterization</atitle><jtitle>IEEE transactions on electron devices</jtitle><stitle>TED</stitle><date>1994-08-01</date><risdate>1994</risdate><volume>41</volume><issue>8</issue><spage>1379</spage><epage>1387</epage><pages>1379-1387</pages><issn>0018-9383</issn><eissn>1557-9646</eissn><coden>IETDAI</coden><abstract>A device isolation structure for low-parasitic bipolar transistor integration is presented. The concept involves two selective epitaxial growth steps (SEG) and two polishing cycles which replace the collector-epitaxy and the deep/shallow trench formation in conventional device isolation. With an optimum device layout, the collector-substrate capacitance is reduced to /spl sime/30%, the collector-base capacitance to /spl sime/70%, and the extrinsic base contact resistance to <50% compared to trench isolation. The combination of SEG and polishing makes it possible to form SOI regions with locally different SOI thicknesses on the same wafer, so that fully depleted CMOS and vertical bipolar transistors can be combined in a SOI-BiCMOS technology.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/16.297733</doi><tpages>9</tpages></addata></record> |
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| identifier | ISSN: 0018-9383 |
| ispartof | IEEE transactions on electron devices, 1994-08, Vol.41 (8), p.1379-1387 |
| issn | 0018-9383 1557-9646 |
| language | eng |
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| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences BiCMOS integrated circuits Bipolar transistors Capacitance Carbon capture and storage CMOS technology Design. Technologies. Operation analysis. Testing Electronics Epitaxial growth Exact sciences and technology Fabrication Integrated circuit interconnections Integrated circuits Isolation technology Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Substrates |
| title | A low-capacitance bipolar/BiCMOS isolation technology. I. Concept, fabrication process, and characterization |
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