A high-performance directly insertable self-aligned ultra-radiation-hard and enhanced isolation field-oxide technology for gigahertz Si-CMOS VLSI
A field-oxide structure for radiation-hard CMOS VLSI is described. It is a three-layer structure consisting of a thin thermal oxide, a doped polysilicon sheet deposited on the thin oxide, and a thick CVD oxide layer deposited on the polysilicon. The polysilicon sheet is maintained at the substrate p...
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Veröffentlicht in: | IEEE electron device letters 1989-01, Vol.10 (1), p.17-19 |
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creator | Manchanda, L. Hillenius, S.J. Lynch, W.T. Cong, H.I. |
description | A field-oxide structure for radiation-hard CMOS VLSI is described. It is a three-layer structure consisting of a thin thermal oxide, a doped polysilicon sheet deposited on the thin oxide, and a thick CVD oxide layer deposited on the polysilicon. The polysilicon sheet is maintained at the substrate potential by, e.g. using n-type poly-Si over the n-tub and p-type poly-Si over the p-tub or p-substrate and allowing contacts to be made through the thin oxide. The small effective electrical thickness of the thin oxide combined with the ground potential of the polysilicon enhances the radiation hardness and maintains good isolation even at radiation levels as high as 10/sup 8/ rads and above. This structure is self-aligned to the active regions and directly insertable into a submicrometer CMOS VLSI without any changes in the circuit design. The circuits made with this technology can operate at 2.5-3 GHz even after a total dose of 50-100 Mrad.< > |
doi_str_mv | 10.1109/55.31667 |
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It is a three-layer structure consisting of a thin thermal oxide, a doped polysilicon sheet deposited on the thin oxide, and a thick CVD oxide layer deposited on the polysilicon. The polysilicon sheet is maintained at the substrate potential by, e.g. using n-type poly-Si over the n-tub and p-type poly-Si over the p-tub or p-substrate and allowing contacts to be made through the thin oxide. The small effective electrical thickness of the thin oxide combined with the ground potential of the polysilicon enhances the radiation hardness and maintains good isolation even at radiation levels as high as 10/sup 8/ rads and above. This structure is self-aligned to the active regions and directly insertable into a submicrometer CMOS VLSI without any changes in the circuit design. The circuits made with this technology can operate at 2.5-3 GHz even after a total dose of 50-100 Mrad.< ></description><identifier>ISSN: 0741-3106</identifier><identifier>EISSN: 1558-0563</identifier><identifier>DOI: 10.1109/55.31667</identifier><identifier>CODEN: EDLEDZ</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Circuit synthesis ; CMOS process ; CMOS technology ; Contacts ; Electronics ; Exact sciences and technology ; Integrated circuit technology ; Integrated circuits ; Isolation technology ; MOS devices ; MOSFETs ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Threshold voltage ; Very large scale integration</subject><ispartof>IEEE electron device letters, 1989-01, Vol.10 (1), p.17-19</ispartof><rights>1989 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c365t-3c9c2951320e7cf21b7cf5cfcfc425de391fbe5c3d76449367f2220aaa928e733</citedby><cites>FETCH-LOGICAL-c365t-3c9c2951320e7cf21b7cf5cfcfc425de391fbe5c3d76449367f2220aaa928e733</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/31667$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,792,4010,27900,27901,27902,54733</link.rule.ids><linktorsrc>$$Uhttps://ieeexplore.ieee.org/document/31667$$EView_record_in_IEEE$$FView_record_in_$$GIEEE</linktorsrc><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&idt=7257937$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Manchanda, L.</creatorcontrib><creatorcontrib>Hillenius, S.J.</creatorcontrib><creatorcontrib>Lynch, W.T.</creatorcontrib><creatorcontrib>Cong, H.I.</creatorcontrib><title>A high-performance directly insertable self-aligned ultra-radiation-hard and enhanced isolation field-oxide technology for gigahertz Si-CMOS VLSI</title><title>IEEE electron device letters</title><addtitle>LED</addtitle><description>A field-oxide structure for radiation-hard CMOS VLSI is described. It is a three-layer structure consisting of a thin thermal oxide, a doped polysilicon sheet deposited on the thin oxide, and a thick CVD oxide layer deposited on the polysilicon. The polysilicon sheet is maintained at the substrate potential by, e.g. using n-type poly-Si over the n-tub and p-type poly-Si over the p-tub or p-substrate and allowing contacts to be made through the thin oxide. The small effective electrical thickness of the thin oxide combined with the ground potential of the polysilicon enhances the radiation hardness and maintains good isolation even at radiation levels as high as 10/sup 8/ rads and above. This structure is self-aligned to the active regions and directly insertable into a submicrometer CMOS VLSI without any changes in the circuit design. The circuits made with this technology can operate at 2.5-3 GHz even after a total dose of 50-100 Mrad.< ></description><subject>Applied sciences</subject><subject>Circuit synthesis</subject><subject>CMOS process</subject><subject>CMOS technology</subject><subject>Contacts</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Integrated circuit technology</subject><subject>Integrated circuits</subject><subject>Isolation technology</subject><subject>MOS devices</subject><subject>MOSFETs</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Threshold voltage</subject><subject>Very large scale integration</subject><issn>0741-3106</issn><issn>1558-0563</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1989</creationdate><recordtype>article</recordtype><recordid>eNqNkU9rGzEQxUVJoE5S6LU3HULpRan-y3sMpk0CLjm47XWRpdGugrxypTXE-Rb9xlnHIecwMHN4P96DeQh9ZvSKMdp8V-pKMK3NBzRjSs0JVVqcoBk1khHBqP6Izmp9oJRJaeQM_b_Gfex6soUSctnYwQH2sYAb0x7HoUIZ7ToBrpACsSl2A3i8S2OxpFgf7RjzQHpbPLaDxzD0BwePY83pRcMhQvIkP0YPeATXDznlbo-nMNzFzvZTwBNeRbL4db_Cf5eruwt0Gmyq8On1nqM_P3_8XtyS5f3N3eJ6SZzQaiTCNY43iglOwbjA2XrayoVpJFceRMPCGpQT3mgpG6FN4JxTa23D52CEOEdfj77bkv_toI7tJlYHKdkB8q62fC64lvwdoOJScSXfBTJB9QR-O4Ku5FoLhHZb4saWfctoe2ixVap9aXFCL189bXU2hTL9N9Y33nBlGnHAvhyxCABv6tHiGZ2YpVs</recordid><startdate>198901</startdate><enddate>198901</enddate><creator>Manchanda, L.</creator><creator>Hillenius, S.J.</creator><creator>Lynch, W.T.</creator><creator>Cong, H.I.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>8FD</scope><scope>H8D</scope><scope>L7M</scope><scope>7SP</scope></search><sort><creationdate>198901</creationdate><title>A high-performance directly insertable self-aligned ultra-radiation-hard and enhanced isolation field-oxide technology for gigahertz Si-CMOS VLSI</title><author>Manchanda, L. ; Hillenius, S.J. ; Lynch, W.T. ; Cong, H.I.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c365t-3c9c2951320e7cf21b7cf5cfcfc425de391fbe5c3d76449367f2220aaa928e733</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1989</creationdate><topic>Applied sciences</topic><topic>Circuit synthesis</topic><topic>CMOS process</topic><topic>CMOS technology</topic><topic>Contacts</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Integrated circuit technology</topic><topic>Integrated circuits</topic><topic>Isolation technology</topic><topic>MOS devices</topic><topic>MOSFETs</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Threshold voltage</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Manchanda, L.</creatorcontrib><creatorcontrib>Hillenius, S.J.</creatorcontrib><creatorcontrib>Lynch, W.T.</creatorcontrib><creatorcontrib>Cong, H.I.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Technology Research Database</collection><collection>Aerospace Database</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Electronics & Communications Abstracts</collection><jtitle>IEEE electron device letters</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Manchanda, L.</au><au>Hillenius, S.J.</au><au>Lynch, W.T.</au><au>Cong, H.I.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>A high-performance directly insertable self-aligned ultra-radiation-hard and enhanced isolation field-oxide technology for gigahertz Si-CMOS VLSI</atitle><jtitle>IEEE electron device letters</jtitle><stitle>LED</stitle><date>1989-01</date><risdate>1989</risdate><volume>10</volume><issue>1</issue><spage>17</spage><epage>19</epage><pages>17-19</pages><issn>0741-3106</issn><eissn>1558-0563</eissn><coden>EDLEDZ</coden><abstract>A field-oxide structure for radiation-hard CMOS VLSI is described. It is a three-layer structure consisting of a thin thermal oxide, a doped polysilicon sheet deposited on the thin oxide, and a thick CVD oxide layer deposited on the polysilicon. The polysilicon sheet is maintained at the substrate potential by, e.g. using n-type poly-Si over the n-tub and p-type poly-Si over the p-tub or p-substrate and allowing contacts to be made through the thin oxide. The small effective electrical thickness of the thin oxide combined with the ground potential of the polysilicon enhances the radiation hardness and maintains good isolation even at radiation levels as high as 10/sup 8/ rads and above. This structure is self-aligned to the active regions and directly insertable into a submicrometer CMOS VLSI without any changes in the circuit design. The circuits made with this technology can operate at 2.5-3 GHz even after a total dose of 50-100 Mrad.< ></abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/55.31667</doi><tpages>3</tpages></addata></record> |
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subjects | Applied sciences Circuit synthesis CMOS process CMOS technology Contacts Electronics Exact sciences and technology Integrated circuit technology Integrated circuits Isolation technology MOS devices MOSFETs Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Threshold voltage Very large scale integration |
title | A high-performance directly insertable self-aligned ultra-radiation-hard and enhanced isolation field-oxide technology for gigahertz Si-CMOS VLSI |
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