A high resolution frequency multiplier for clock signal generation

This paper presents a high resolution frequency multiplier (FMUL) with the ability to multiply frequency with a programmable high multiplication factor, in the order of 10/sup 2/-10/sup 4/ and of the form N/M. It was designed for chip-sets that use a real time clock (32768 Hz) for power-save operati...

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Veröffentlicht in:	IEEE journal of solid-state circuits 1996-07, Vol.31 (7), p.1059-1062
Hauptverfasser:	Fried, R., Rosin, E.
Format:	Artikel
Sprache:	eng
Schlagworte:	Circuits Clocks Digital control Frequency Oscillators Phase locked loops Signal generators Signal resolution Tuning Voltage
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