Dynamic data retention and implied design criteria for floating-body SOI DRAM

Dynamic data retention and implied design criteria for floating-body SOI DRAM

A physical MOSFET model in SOISPICE is used to characterize dynamic data retention in PD/SOI DRAM cells. Simulations show that transient parasitic BJT current underlies peculiar data retention, and they suggest how periodic body discharge effected by data refresh with a high flatband-voltage cell tr...

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Veröffentlicht in:IEEE electron device letters 1996-08, Vol.17 (8), p.385-387
Hauptverfasser: Dongwook Suh, Fossum, J.G., Pelella, M.M.
Format: Artikel
Sprache:eng
Schlagworte:
Coupling circuits
Equations
Hysteresis
Microelectronics
MOSFET circuits
Partial discharges
Predictive models
Radiative recombination
Random access memory
Threshold voltage
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Zusammenfassung:A physical MOSFET model in SOISPICE is used to characterize dynamic data retention in PD/SOI DRAM cells. Simulations show that transient parasitic BJT current underlies peculiar data retention, and they suggest how periodic body discharge effected by data refresh with a high flatband-voltage cell transistor can render PD/SOI technology viable and attractive for gigabit DRAM applications.
ISSN:0741-3106
1558-0563
DOI:10.1109/55.511583