Data-driven self-timed RSFQ digital integrated circuit and system
A novel asynchronous timing scheme, data-driven self-timing (DDST) is proposed and implemented in Rapid Single-Flux-Quantum (RSFQ) superconductive integrated circuits. In this asynchronous approach, the timing signals are generated from the data and no global clock is needed to drive the RSFQ circui...
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| Veröffentlicht in: | IEEE transactions on applied superconductivity 1997-06, Vol.7 (2), p.3634-3637 |
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| container_end_page | 3637 |
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| container_issue | 2 |
| container_start_page | 3634 |
| container_title | IEEE transactions on applied superconductivity |
| container_volume | 7 |
| creator | Deng, Z.J. Yoshikawa, N. Whiteley, S.R. Van Duzer, T. |
| description | A novel asynchronous timing scheme, data-driven self-timing (DDST) is proposed and implemented in Rapid Single-Flux-Quantum (RSFQ) superconductive integrated circuits. In this asynchronous approach, the timing signals are generated from the data and no global clock is needed to drive the RSFQ circuit and system. The essence of the self-timing scheme is to localize the system timing in order to avoid the overhead of global clock distribution, and to minimize the timing uncertainty. The DDST scheme has been applied to the design of a shift register, a demultiplexor, and a self-timed high speed digital test system. In this paper, test results of a 4-bit DDST shift register and a high speed on-chip clock generator will be presented to demonstrate the successful DDST operation of RSFQ integrated circuits at a rate of 20 Gb/s. |
| doi_str_mv | 10.1109/77.622205 |
| format | Article |
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In this asynchronous approach, the timing signals are generated from the data and no global clock is needed to drive the RSFQ circuit and system. The essence of the self-timing scheme is to localize the system timing in order to avoid the overhead of global clock distribution, and to minimize the timing uncertainty. The DDST scheme has been applied to the design of a shift register, a demultiplexor, and a self-timed high speed digital test system. In this paper, test results of a 4-bit DDST shift register and a high speed on-chip clock generator will be presented to demonstrate the successful DDST operation of RSFQ integrated circuits at a rate of 20 Gb/s.</description><subject>Applied sciences</subject><subject>Circuit testing</subject><subject>Circuits and systems</subject><subject>Clocks</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Digital integrated circuits</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Integrated circuits</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. 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Technologies. Operation analysis. Testing</topic><topic>Digital integrated circuits</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Integrated circuits</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Shift registers</topic><topic>Signal generators</topic><topic>Superconducting devices</topic><topic>Superconducting integrated circuits</topic><topic>Superconductivity</topic><topic>Timing</topic><topic>Uncertainty</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Deng, Z.J.</creatorcontrib><creatorcontrib>Yoshikawa, N.</creatorcontrib><creatorcontrib>Whiteley, S.R.</creatorcontrib><creatorcontrib>Van Duzer, T.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Solid State and Superconductivity Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on applied superconductivity</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Deng, Z.J.</au><au>Yoshikawa, N.</au><au>Whiteley, S.R.</au><au>Van Duzer, T.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Data-driven self-timed RSFQ digital integrated circuit and system</atitle><jtitle>IEEE transactions on applied superconductivity</jtitle><stitle>TASC</stitle><date>1997-06-01</date><risdate>1997</risdate><volume>7</volume><issue>2</issue><spage>3634</spage><epage>3637</epage><pages>3634-3637</pages><issn>1051-8223</issn><eissn>1558-2515</eissn><coden>ITASE9</coden><abstract>A novel asynchronous timing scheme, data-driven self-timing (DDST) is proposed and implemented in Rapid Single-Flux-Quantum (RSFQ) superconductive integrated circuits. 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| identifier | ISSN: 1051-8223 |
| ispartof | IEEE transactions on applied superconductivity, 1997-06, Vol.7 (2), p.3634-3637 |
| issn | 1051-8223 1558-2515 |
| language | eng |
| recordid | cdi_proquest_miscellaneous_28279883 |
| source | IEEE Electronic Library (IEL) |
| subjects | Applied sciences Circuit testing Circuits and systems Clocks Design. Technologies. Operation analysis. Testing Digital integrated circuits Electronics Exact sciences and technology Integrated circuits Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Shift registers Signal generators Superconducting devices Superconducting integrated circuits Superconductivity Timing Uncertainty |
| title | Data-driven self-timed RSFQ digital integrated circuit and system |
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