Design and evaluation of ion-implanted CMOS structures

An IC chip intended for the integrated signal readout of PbS-Si heterojunction detectors has been designed using a p-well/ n-substrate CMOS structure, The chip contains integrated and discrete n-MOSFET readout circuits as well as test structures. The chip fabrication used ion implantation for all doping steps, including the p well. The fabricated device profiles show good agreement with the results of a process analysis performed using the SUPREM program. Among the experimental n-MOSFET characteristics measured were: g_{m} = 230 µmho, \mu_{ch} = 240 cm 2 /V . s, V_{br} \geq 200 V, and N_{ss} = 1.26 \times 10^{11} / cm 2 . eV.