Dynamic degradation in MOSFET' s. II. Application in the circuitenvironment
For pt.I, see ibid., vol.38 no.8, pp.1852-1858, Aug. 1991. The physical effects discussed in Pt.I are classified with respect to real operation of devices in circuits from an engineer's viewpoint. Stress results from different kinds of logic stages are discussed and relations set up between sta...
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Veröffentlicht in: | IEEE transactions on electron devices 1991-08, Vol.38 (8), p.1859-1867 |
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container_title | IEEE transactions on electron devices |
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creator | Weber, W Brox, H M Kunemund, T Muhlhoff, M Schmitt-Landsiedel, D |
description | For pt.I, see ibid., vol.38 no.8, pp.1852-1858, Aug. 1991. The physical effects discussed in Pt.I are classified with respect to real operation of devices in circuits from an engineer's viewpoint. Stress results from different kinds of logic stages are discussed and relations set up between static and dynamic lifetimes. It is shown that within certain limited error boundaries, the static approach is essentially valid as long as stress conditions are considered that are oriented to operation in digital logic. The transmission gate is investigated separately, because in this case specific phenomena caused by bidirectional stress must be considered |
doi_str_mv | 10.1109/16.119026 |
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fullrecord | <record><control><sourceid>proquest</sourceid><recordid>TN_cdi_proquest_miscellaneous_28265062</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>28265062</sourcerecordid><originalsourceid>FETCH-proquest_miscellaneous_282650623</originalsourceid><addsrcrecordid>eNqNjLsKwjAYRjMoWC-Db5BJp9YkraEdxQsWEQfdS0h_NZImtUkF394O4ux0-DgfB6EpJRGlJFtQ3jEjjPdQQAhNwyxO4wEaOvfoJk8SFqDD5m1EpSQu4daIUnhlDVYGH0_n3fYyxy7CeR7hVV1rJX_W3wFL1chWeTAv1VhTgfFj1L8K7WDy5QjNusZ6H9aNfbbgfFEpJ0FrYcC2rmAp40vCWfz38QNCFEHz</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>28265062</pqid></control><display><type>article</type><title>Dynamic degradation in MOSFET' s. II. Application in the circuitenvironment</title><source>IEEE Xplore / Electronic Library Online (IEL)</source><creator>Weber, W ; Brox, H M ; Kunemund, T ; Muhlhoff, M ; Schmitt-Landsiedel, D</creator><creatorcontrib>Weber, W ; Brox, H M ; Kunemund, T ; Muhlhoff, M ; Schmitt-Landsiedel, D</creatorcontrib><description>For pt.I, see ibid., vol.38 no.8, pp.1852-1858, Aug. 1991. The physical effects discussed in Pt.I are classified with respect to real operation of devices in circuits from an engineer's viewpoint. Stress results from different kinds of logic stages are discussed and relations set up between static and dynamic lifetimes. It is shown that within certain limited error boundaries, the static approach is essentially valid as long as stress conditions are considered that are oriented to operation in digital logic. The transmission gate is investigated separately, because in this case specific phenomena caused by bidirectional stress must be considered</description><identifier>ISSN: 0018-9383</identifier><identifier>DOI: 10.1109/16.119026</identifier><language>eng</language><ispartof>IEEE transactions on electron devices, 1991-08, Vol.38 (8), p.1859-1867</ispartof><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><link.rule.ids>314,776,780,27901,27902</link.rule.ids></links><search><creatorcontrib>Weber, W</creatorcontrib><creatorcontrib>Brox, H M</creatorcontrib><creatorcontrib>Kunemund, T</creatorcontrib><creatorcontrib>Muhlhoff, M</creatorcontrib><creatorcontrib>Schmitt-Landsiedel, D</creatorcontrib><title>Dynamic degradation in MOSFET' s. II. Application in the circuitenvironment</title><title>IEEE transactions on electron devices</title><description>For pt.I, see ibid., vol.38 no.8, pp.1852-1858, Aug. 1991. The physical effects discussed in Pt.I are classified with respect to real operation of devices in circuits from an engineer's viewpoint. Stress results from different kinds of logic stages are discussed and relations set up between static and dynamic lifetimes. It is shown that within certain limited error boundaries, the static approach is essentially valid as long as stress conditions are considered that are oriented to operation in digital logic. The transmission gate is investigated separately, because in this case specific phenomena caused by bidirectional stress must be considered</description><issn>0018-9383</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1991</creationdate><recordtype>article</recordtype><recordid>eNqNjLsKwjAYRjMoWC-Db5BJp9YkraEdxQsWEQfdS0h_NZImtUkF394O4ux0-DgfB6EpJRGlJFtQ3jEjjPdQQAhNwyxO4wEaOvfoJk8SFqDD5m1EpSQu4daIUnhlDVYGH0_n3fYyxy7CeR7hVV1rJX_W3wFL1chWeTAv1VhTgfFj1L8K7WDy5QjNusZ6H9aNfbbgfFEpJ0FrYcC2rmAp40vCWfz38QNCFEHz</recordid><startdate>19910801</startdate><enddate>19910801</enddate><creator>Weber, W</creator><creator>Brox, H M</creator><creator>Kunemund, T</creator><creator>Muhlhoff, M</creator><creator>Schmitt-Landsiedel, D</creator><scope>7SP</scope><scope>8FD</scope><scope>L7M</scope></search><sort><creationdate>19910801</creationdate><title>Dynamic degradation in MOSFET' s. II. Application in the circuitenvironment</title><author>Weber, W ; Brox, H M ; Kunemund, T ; Muhlhoff, M ; Schmitt-Landsiedel, D</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-proquest_miscellaneous_282650623</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1991</creationdate><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Weber, W</creatorcontrib><creatorcontrib>Brox, H M</creatorcontrib><creatorcontrib>Kunemund, T</creatorcontrib><creatorcontrib>Muhlhoff, M</creatorcontrib><creatorcontrib>Schmitt-Landsiedel, D</creatorcontrib><collection>Electronics & Communications Abstracts</collection><collection>Technology Research Database</collection><collection>Advanced Technologies Database with Aerospace</collection><jtitle>IEEE transactions on electron devices</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Weber, W</au><au>Brox, H M</au><au>Kunemund, T</au><au>Muhlhoff, M</au><au>Schmitt-Landsiedel, D</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>Dynamic degradation in MOSFET' s. II. Application in the circuitenvironment</atitle><jtitle>IEEE transactions on electron devices</jtitle><date>1991-08-01</date><risdate>1991</risdate><volume>38</volume><issue>8</issue><spage>1859</spage><epage>1867</epage><pages>1859-1867</pages><issn>0018-9383</issn><abstract>For pt.I, see ibid., vol.38 no.8, pp.1852-1858, Aug. 1991. The physical effects discussed in Pt.I are classified with respect to real operation of devices in circuits from an engineer's viewpoint. Stress results from different kinds of logic stages are discussed and relations set up between static and dynamic lifetimes. It is shown that within certain limited error boundaries, the static approach is essentially valid as long as stress conditions are considered that are oriented to operation in digital logic. The transmission gate is investigated separately, because in this case specific phenomena caused by bidirectional stress must be considered</abstract><doi>10.1109/16.119026</doi></addata></record> |
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title | Dynamic degradation in MOSFET' s. II. Application in the circuitenvironment |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-29T08%3A21%3A29IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=Dynamic%20degradation%20in%20MOSFET'%20s.%20II.%20Application%20in%20the%20circuitenvironment&rft.jtitle=IEEE%20transactions%20on%20electron%20devices&rft.au=Weber,%20W&rft.date=1991-08-01&rft.volume=38&rft.issue=8&rft.spage=1859&rft.epage=1867&rft.pages=1859-1867&rft.issn=0018-9383&rft_id=info:doi/10.1109/16.119026&rft_dat=%3Cproquest%3E28265062%3C/proquest%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_pqid=28265062&rft_id=info:pmid/&rfr_iscdi=true |