Design and implementation of a lossless parallel high-speed data compression system

Logic density increases have made feasible the implementation of multiprocessor systems able to meet the intensive data processing demands of highly concurrent systems. We describe the research and hardware implementation of a high-performance parallel multicompressor chip. A detailed investigation...

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Veröffentlicht in:	IEEE transactions on parallel and distributed systems 2004-06, Vol.15 (6), p.481-490
Hauptverfasser:	Milward, M., Nunez, J.L., Mulvaney, D.
Format:	Artikel
Sprache:	eng
Schlagworte:	Bandwidth Communication networks Compressing Compressors Computer networks Data compression Demand Density Design engineering Devices Engines Field programmable gate arrays FPGA Hardware Logic Lossless data compression Marketing Multiple Compressors Routing Throughput X-MatchProRli
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