A defect-tolerant memory architecture for molecular electronics

This paper presents a defect-tolerant memory architecture for molecular electronics. A crossbar structure, where molecules are sandwiched between nanowires, is used as a model to realize molecular memory and to achieve defect tolerance. Defects in the logic circuits for addressing memory are also ta...

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Veröffentlicht in:	IEEE transactions on nanotechnology 2004-03, Vol.3 (1), p.152-157
Hauptverfasser:	Lee, M.-H., Kim, Y.K., Choi, Y.-H.
Format:	Artikel
Sprache:	eng
Schlagworte:	Applied sciences Architecture Circuit properties Circuit testing Computer simulation Defects Digital circuits Electric, optical and optoelectronic circuits Electronic circuits Electronics Exact sciences and technology Logic circuits Logic devices Logic functions Memory architecture Molecular electronics Molecular electronics, nanoelectronics Molecular structure Multiplexing Nanotechnology Nanowires Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices Switches Tolerances Wires
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Beschreibung
Zusammenfassung:	This paper presents a defect-tolerant memory architecture for molecular electronics. A crossbar structure, where molecules are sandwiched between nanowires, is used as a model to realize molecular memory and to achieve defect tolerance. Defects in the logic circuits for addressing memory are also taken into account. The number of spare rows and columns to form a functioning memory is estimated by computer simulation for various values of defect rate and memory size.
ISSN:	1536-125X 1941-0085
DOI:	10.1109/TNANO.2004.824011